def __init__(self, data_width):
self.submodules.host = Host(data_width, root_id, endpoint_id,
phy_debug = False,
chipset_debug = False,
chipset_split = True,
chipset_reordering = True,
host_debug = True)
# Endpoint -------------------------------------------------------------------------
self.submodules.endpoint = LitePCIeEndpoint(self.host.phy, max_pending_requests=8)
# DMA Reader/Writer ----------------------------------------------------------------
dma_reader_port = self.endpoint.crossbar.get_master_port(read_only=True)
dma_writer_port = self.endpoint.crossbar.get_master_port(write_only=True)
self.submodules.dma_reader = LitePCIeDMAReader(self.endpoint, dma_reader_port)
self.submodules.dma_writer = LitePCIeDMAWriter(self.endpoint, dma_writer_port)
self.comb += self.dma_reader.source.connect(self.dma_writer.sink)
# MSI ------------------------------------------------------------------------------
self.submodules.msi = LitePCIeMSI(2)
self.comb += [
self.msi.irqs[log2_int(DMA_READER_IRQ)].eq(self.dma_reader.irq),
self.msi.irqs[log2_int(DMA_WRITER_IRQ)].eq(self.dma_writer.irq)
]
self.submodules.msi_handler = MSIHandler(debug=False)
self.comb += self.msi.source.connect(self.msi_handler.sink)
def __init__(self, with_converter=False):
self.submodules.host = Host(64, root_id, endpoint_id,
phy_debug=False,
chipset_debug=False, chipset_split=True, chipset_reordering=True,
host_debug=True)
self.submodules.endpoint = LitePCIeEndpoint(self.host.phy, max_pending_requests=8, with_reordering=True)
self.submodules.dma_reader = LitePCIeDMAReader(self.endpoint, self.endpoint.crossbar.get_master_port(read_only=True))
self.submodules.dma_writer = LitePCIeDMAWriter(self.endpoint, self.endpoint.crossbar.get_master_port(write_only=True))
if with_converter:
self.submodules.up_converter = stream.StrideConverter(dma_layout(16), dma_layout(64))
self.submodules.down_converter = stream.StrideConverter(dma_layout(64), dma_layout(16))
self.submodules += stream.Pipeline(self.dma_reader,
self.down_converter,
self.up_converter,
self.dma_writer)
else:
self.comb += self.dma_reader.source.connect(self.dma_writer.sink)
self.submodules.msi = LitePCIeMSI(2)
self.comb += [
self.msi.irqs[log2_int(DMA_READER_IRQ)].eq(self.dma_reader.irq),
self.msi.irqs[log2_int(DMA_WRITER_IRQ)].eq(self.dma_writer.irq)
]
self.submodules.irq_handler = InterruptHandler(debug=False)
self.comb += self.msi.source.connect(self.irq_handler.sink)