def __init__(self):
self.submodules.hdd0 = HDD(n=0,
link_debug = False,
link_random_level = 0,
transport_debug = False,
transport_loopback = False,
hdd_debug = True)
self.submodules.core0 = LiteSATACore(self.hdd0.phy)
self.submodules.hdd1 = HDD(n=1,
link_debug = False,
link_random_level = 0,
transport_debug = False,
transport_loopback = False,
hdd_debug = True)
self.submodules.core1 = LiteSATACore(self.hdd1.phy)
self.submodules.mirroring = LiteSATAMirroring([self.core0, self.core1])
self.submodules.crossbar0 = LiteSATACrossbar(self.mirroring.ports[0])
self.submodules.generator0 = LiteSATABISTGenerator(self.crossbar0.get_port())
self.submodules.checker0 = LiteSATABISTChecker(self.crossbar0.get_port())
self.submodules.crossbar1 = LiteSATACrossbar(self.mirroring.ports[1])
self.submodules.generator1 = LiteSATABISTGenerator(self.crossbar1.get_port())
self.submodules.checker1 = LiteSATABISTChecker(self.crossbar1.get_port())
def __init__(self, dw=32):
self.submodules.hdd = HDD(
link_debug=False, link_random_level=0,
transport_debug=False, transport_loopback=False,
hdd_debug=True)
self.submodules.core = LiteSATACore(self.hdd.phy)
self.submodules.crossbar = LiteSATACrossbar(self.core)
self.submodules.generator = LiteSATABISTGenerator(self.crossbar.get_port(dw))
self.submodules.checker = LiteSATABISTChecker(self.crossbar.get_port(dw))
def __init__(self, platform, revision="sata_gen3", trx_dw=16):
clk_freq = 200 * 1000000
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteSATA example design",
with_timer=False)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform)
# SATA PHY/Core/Frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device,
platform.request("sata_clocks"),
platform.request("sata", 0),
revision, clk_freq, trx_dw)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar,
with_csr=True)
# Status Leds
self.submodules.leds = StatusLeds(platform, self.sata_phy)
self.specials += [
Keep(ClockSignal("sata_rx")),
Keep(ClockSignal("sata_tx"))
]
platform.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk]
create_clock -name sata_rx_clk -period {sata_clk_period} [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period {sata_clk_period} [get_nets sata_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
""".format(sata_clk_period="3.3" if trx_dw == 16 else "6.6"))
def __init__(self, platform, revision="sata_gen2", data_width=16):
sys_clk_freq = int(100e6)
SoCCore.__init__(self,
platform,
sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteSATA example design",
ident_version=True,
with_timer=False)
self.add_cpu(
UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu.wishbone)
self.submodules.crg = CRG(platform)
# SATA PHY/Core/Frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device,
platform.request("sata_clocks"),
platform.request("sata",
0), revision,
sys_clk_freq, data_width)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar,
with_csr=True)
# Status Leds
self.submodules.leds = StatusLeds(platform, self.sata_phy)
self.sata_phy.crg.cd_sata_rx.clk.attr.add("keep")
self.sata_phy.crg.cd_sata_tx.clk.attr.add("keep")
platform.add_platform_command("""
create_clock -name sys_clk -period 10 [get_nets sys_clk]
create_clock -name sata_rx_clk -period {sata_clk_period} [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period {sata_clk_period} [get_nets sata_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
""".format(sata_clk_period="6.6" if data_width == 16 else "13.2"))
def __init__(self, platform, revision="sata_gen3", data_width=16):
sys_clk_freq = int(200e6)
SoCMini.__init__(self,
platform,
sys_clk_freq,
csr_data_width=32,
ident="LiteSATA example design",
ident_version=True)
# Serial Bridge ----------------------------------------------------------------------------
self.submodules.bridge = UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200)
self.add_wb_master(self.bridge.wishbone)
self.submodules.crg = CRG(platform)
# SATA PHY/Core/Frontend -------------------------------------------------------------------
self.submodules.sata_phy = LiteSATAPHY(platform.device,
platform.request("sata_clocks"),
platform.request("sata",
0), revision,
sys_clk_freq, data_width)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar,
with_csr=True)
self.add_csr("sata_bist")
# Status Leds ------------------------------------------------------------------------------
self.submodules.leds = StatusLeds(platform, self.sata_phy)
# Timing constraints -----------------------------------------------------------------------
self.sata_phy.crg.cd_sata_rx.clk.attr.add("keep")
self.sata_phy.crg.cd_sata_tx.clk.attr.add("keep")
platform.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk]
create_clock -name sata_rx_clk -period {sata_clk_period} [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period {sata_clk_period} [get_nets sata_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
""".format(sata_clk_period="3.3" if data_width == 16 else "6.6"))
def __init__(self):
self.submodules.hdd0 = HDD(n=0,
link_debug = False,
link_random_level = 0,
transport_debug = False,
transport_loopback = False,
hdd_debug = True)
self.submodules.core0 = LiteSATACore(self.hdd0.phy)
self.submodules.hdd1 = HDD(n=1,
link_debug = False,
link_random_level = 0,
transport_debug = False,
transport_loopback = False,
hdd_debug = True)
self.submodules.core1 = LiteSATACore(self.hdd1.phy)
self.submodules.striping = LiteSATAStriping([self.core0, self.core1])
self.submodules.crossbar = LiteSATACrossbar(self.striping)
self.submodules.generator = LiteSATABISTGenerator(self.crossbar.get_port())
self.submodules.checker = LiteSATABISTChecker(self.crossbar.get_port())
def __init__(self,
platform,
gen="gen2",
with_pll_refclk=True,
with_analyzer=False):
assert gen in ["gen1", "gen2"]
sys_clk_freq = int(100e6)
sata_clk_freq = {"gen1": 75e6, "gen2": 150e6}[gen]
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
sys_clk_freq,
ident="LiteSATA bench on Nexys Video",
ident_version=True,
with_uart=True,
uart_name="bridge")
# SATA -------------------------------------------------------------------------------------
if with_pll_refclk:
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
refclk=None if not with_pll_refclk else self.cd_sata_refclk.clk,
pads=platform.request("fmc2sata"),
gen=gen,
clk_freq=sys_clk_freq,
data_width=16)
self.add_csr("sata_phy")
# Core
self.submodules.sata_core = LiteSATACore(self.sata_phy)
# Crossbar
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
# BIST
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar,
with_csr=True)
self.add_csr("sata_bist")
# Timing constraints
platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk,
1e9 / sata_clk_freq)
platform.add_period_constraint(self.sata_phy.crg.cd_sata_rx.clk,
1e9 / sata_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.sata_phy.crg.cd_sata_tx.clk,
self.sata_phy.crg.cd_sata_rx.clk)
# Leds -------------------------------------------------------------------------------------
# sys_clk
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led", 0).eq(sys_counter[26])
# tx_clk
tx_counter = Signal(32)
self.sync.sata_tx += tx_counter.eq(tx_counter + 1)
self.comb += platform.request("user_led", 1).eq(tx_counter[26])
# rx_clk
rx_counter = Signal(32)
self.sync.sata_rx += rx_counter.eq(rx_counter + 1)
self.comb += platform.request("user_led", 2).eq(rx_counter[26])
# ready
self.comb += platform.request("user_led",
3).eq(self.sata_phy.ctrl.ready)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
self.sata_phy.phy.tx_init.fsm,
self.sata_phy.phy.rx_init.fsm,
self.sata_phy.ctrl.fsm,
self.sata_phy.ctrl.ready,
self.sata_phy.source,
self.sata_phy.sink,
self.sata_core.command.sink,
self.sata_core.command.source,
self.sata_core.link.rx.fsm,
self.sata_core.link.tx.fsm,
self.sata_core.transport.rx.fsm,
self.sata_core.transport.tx.fsm,
self.sata_core.command.rx.fsm,
self.sata_core.command.tx.fsm,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 512, csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(self,
platform,
connector="qsfp",
gen="gen2",
with_analyzer=False):
assert connector in ["qsfp", "pcie"]
assert gen in ["gen1", "gen2", "gen3"]
sys_clk_freq = int(187.5e6)
sata_clk_freq = {"gen1": 75e6, "gen2": 150e6, "gen3": 300e6}[gen]
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
sys_clk_freq,
ident="LiteSATA bench on XCU1525",
ident_version=True,
with_uart=True,
uart_name="bridge")
# SATA -------------------------------------------------------------------------------------
# RefClk / Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6, buf=None)
sata_refclk = ClockSignal("sata_refclk")
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
refclk=sata_refclk,
pads=platform.request(connector + "2sata"),
gen=gen,
clk_freq=sys_clk_freq,
data_width=16)
self.add_csr("sata_phy")
# Core
self.submodules.sata_core = LiteSATACore(self.sata_phy)
# Crossbar
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
# BIST
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar,
with_csr=True)
self.add_csr("sata_bist")
# Timing constraints
platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk,
1e9 / sata_clk_freq)
platform.add_period_constraint(self.sata_phy.crg.cd_sata_rx.clk,
1e9 / sata_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.sata_phy.crg.cd_sata_tx.clk,
self.sata_phy.crg.cd_sata_rx.clk)
# Leds -------------------------------------------------------------------------------------
# sys_clk
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led", 0).eq(sys_counter[26])
# rx_clk
rx_counter = Signal(32)
self.sync.sata_rx += rx_counter.eq(rx_counter + 1)
self.comb += platform.request("user_led", 1).eq(rx_counter[26])
# ready
self.comb += platform.request("user_led",
2).eq(self.sata_phy.ctrl.ready)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
self.sata_phy.phy.tx_init.fsm,
self.sata_phy.phy.rx_init.fsm,
self.sata_phy.ctrl.fsm,
self.sata_phy.ctrl.ready,
self.sata_phy.source,
self.sata_phy.sink,
self.sata_core.command.sink,
self.sata_core.command.source,
self.sata_core.link.rx.fsm,
self.sata_core.link.tx.fsm,
self.sata_core.transport.rx.fsm,
self.sata_core.transport.tx.fsm,
self.sata_core.command.rx.fsm,
self.sata_core.command.tx.fsm,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 512, csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(self,
platform,
design="base",
clk_freq=200 * 1000000,
nports=1,
ports_dw=32):
self.clk_freq = clk_freq
self.clock_domains.cd_sys = ClockDomain()
self.comb += [
self.cd_sys.clk.eq(platform.request("sys_clock")),
self.cd_sys.rst.eq(platform.request("sys_reset"))
]
if design == "base" or design == "bist":
# SATA PHY/Core/frontend
self.submodules.sata_phy = LiteSATAPHY(
platform.device, platform.request("sata_clocks"),
platform.request("sata"), "sata_gen3", clk_freq)
self.sata_phys = [self.sata_phy]
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
if design == "bist":
# BIST
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar)
generator = self.sata_bist.generator
generator_pads = platform.request("generator")
self.comb += [
generator.start.eq(generator_pads.start),
generator.sector.eq(generator_pads.sector),
generator.count.eq(generator_pads.count),
generator.random.eq(generator_pads.random),
generator_pads.done.eq(generator.done),
generator_pads.aborted.eq(generator.aborted),
generator_pads.errors.eq(generator.errors)
]
checker = self.sata_bist.checker
checker_pads = platform.request("checker")
self.comb += [
checker.start.eq(checker_pads.start),
checker.sector.eq(checker_pads.sector),
checker.count.eq(checker_pads.count),
checker.random.eq(checker_pads.random),
checker_pads.done.eq(checker.done),
checker_pads.aborted.eq(checker.aborted),
checker_pads.errors.eq(checker.errors),
]
identify = self.sata_bist.identify
identify_pads = platform.request("identify")
self.comb += [
identify.start.eq(identify_pads.start),
identify_pads.done.eq(identify.done),
identify_pads.source_valid.eq(identify.source.valid),
identify_pads.source_data.eq(identify.source.data),
identify.source.ready.eq(identify_pads.source_ready)
]
self.specials += [
Keep(ClockSignal("sata_rx")),
Keep(ClockSignal("sata_tx"))
]
elif design == "striping":
self.nphys = 4
# SATA PHYs
self.sata_phys = []
for i in range(self.nphys):
sata_phy = LiteSATAPHY(
platform.device,
platform.request("sata_clocks")
if i == 0 else self.sata_phys[0].crg.refclk,
platform.request("sata", i), "sata_gen3", clk_freq)
sata_phy = ClockDomainsRenamer({
"sata_rx":
"sata_rx{}".format(str(i)),
"sata_tx":
"sata_tx{}".format(str(i))
})(sata_phy)
setattr(self.submodules, "sata_phy{}".format(str(i)), sata_phy)
self.sata_phys.append(sata_phy)
# SATA Cores
self.sata_cores = []
for i in range(self.nphys):
sata_core = LiteSATACore(self.sata_phys[i])
setattr(self.submodules, "sata_core{}".format(str(i)),
sata_core)
self.sata_cores.append(sata_core)
# SATA Frontend
self.submodules.sata_striping = LiteSATAStriping(self.sata_cores)
self.submodules.sata_crossbar = LiteSATACrossbar(
self.sata_striping)
for i in range(len(self.sata_phys)):
self.specials += [
Keep(ClockSignal("sata_rx{}".format(str(i)))),
Keep(ClockSignal("sata_tx{}".format(str(i))))
]
else:
ValueError("Unknown design " + design)
# CRG / Ctrl ready
crg_ready_pads = platform.request("crg_ready")
ctrl_ready_pads = platform.request("ctrl_ready")
for i, sata_phy in enumerate(self.sata_phys):
self.comb += [
crg_ready_pads[i].eq(sata_phy.crg.ready),
ctrl_ready_pads[i].eq(sata_phy.ctrl.ready)
]
# Get user ports from crossbar
self.user_ports = self.sata_crossbar.get_ports(nports, ports_dw)
for i, user_port in enumerate(self.user_ports):
user_port_pads = platform.request("user_port", i + 1)
self.comb += [
user_port.sink.valid.eq(user_port_pads.sink_valid),
user_port.sink.last.eq(user_port_pads.sink_last),
user_port.sink.write.eq(user_port_pads.sink_write),
user_port.sink.read.eq(user_port_pads.sink_read),
user_port.sink.identify.eq(user_port_pads.sink_identify),
user_port.sink.sector.eq(user_port_pads.sink_sector),
user_port.sink.count.eq(user_port_pads.sink_count),
user_port_pads.sink_ready.eq(user_port.sink.ready),
]
self.comb += [
user_port_pads.source_valid.eq(user_port.source.valid),
user_port_pads.source_last.eq(user_port.source.last),
user_port_pads.source_write.eq(user_port.source.write),
user_port_pads.source_read.eq(user_port.source.read),
user_port_pads.source_identify.eq(user_port.source.identify),
user_port_pads.source_end.eq(user_port.source.end),
user_port_pads.source_failed.eq(user_port.source.failed),
user_port_pads.source_data.eq(user_port.source.data),
user_port.source.ready.eq(user_port_pads.source_ready),
]
def __init__(self, platform, revision="sata_gen3", data_width=16, nphys=4):
self.nphys = nphys
sys_clk_freq = int(200e6)
SoCMini.__init__(self,
platform,
sys_clk_freq,
csr_data_width=32,
ident="LiteSATA example design",
ident_version=True)
# Serial Bridge ----------------------------------------------------------------------------
self.submodules.bridge = UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200)
self.add_wb_master(self.bridge.wishbone)
self.submodules.crg = CRG(platform)
# SATA PHYs --------------------------------------------------------------------------------
self.sata_phys = []
for i in range(self.nphys):
sata_phy = LiteSATAPHY(
platform.device,
platform.request("sata_clocks")
if i == 0 else self.sata_phys[0].crg.refclk,
platform.request("sata", i), revision, sys_clk_freq,
data_width)
sata_phy = ClockDomainsRenamer({
"sata_rx":
"sata_rx{}".format(str(i)),
"sata_tx":
"sata_tx{}".format(str(i))
})(sata_phy)
setattr(self.submodules, "sata_phy{}".format(str(i)), sata_phy)
self.sata_phys.append(sata_phy)
# SATA Cores -------------------------------------------------------------------------------
self.sata_cores = []
for i in range(self.nphys):
sata_core = LiteSATACore(self.sata_phys[i])
setattr(self.submodules, "sata_core{}".format(str(i)), sata_core)
self.sata_cores.append(sata_core)
# SATA Frontend ----------------------------------------------------------------------------
self.submodules.sata_mirroring = LiteSATAMirroring(self.sata_cores)
self.sata_crossbars = []
for i in range(self.nphys):
sata_crossbar = LiteSATACrossbar(self.sata_mirroring.ports[i])
setattr(self.submodules, "sata_crossbar{}".format(str(i)),
sata_crossbar)
self.sata_crossbars.append(sata_crossbar)
# SATA Application -------------------------------------------------------------------------
self.sata_bists = []
for i in range(self.nphys):
sata_bist = LiteSATABIST(self.sata_crossbars[i], with_csr=True)
setattr(self.submodules, "sata_bist{}".format(str(i)), sata_bist)
self.sata_bists.append(sata_bist)
self.add_csr("sata_bist" + str(i))
# Status Leds ------------------------------------------------------------------------------
self.submodules.status_leds = StatusLeds(platform, self.sata_phys)
# Timing constraints -----------------------------------------------------------------------
platform.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk]
""")
for i in range(len(self.sata_phys)):
self.sata_phys[i].crg.cd_sata_rx.clk.attr.add("keep")
self.sata_phys[i].crg.cd_sata_tx.clk.attr.add("keep")
platform.add_platform_command("""
create_clock -name {sata_rx_clk} -period {sata_clk_period} [get_nets {sata_rx_clk}]
create_clock -name {sata_tx_clk} -period {sata_clk_period} [get_nets {sata_tx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}]
set_false_path -from [get_clocks {sata_rx_clk}] -to [get_clocks sys_clk]
set_false_path -from [get_clocks {sata_tx_clk}] -to [get_clocks sys_clk]
""".format(sata_rx_clk="sata_rx{}_clk".format(str(i)),
sata_tx_clk="sata_tx{}_clk".format(str(i)),
sata_clk_period="3.3" if data_width == 16 else "6.6"))
def __init__(self, platform, core_config):
platform.add_extension(get_sata_ios())
platform.add_extension(get_ctrl_ios())
sys_clk_freq = int(float(core_config.get("clk_freq")))
sata_clk_freq = {"gen1": 75e6, "gen2": 150e6, "gen3": 300e6}[core_config["gen"]]
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
csr_data_width = 32,
ident = "LiteSATA standalone core",
ident_version = True
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = LiteSATACRG(platform, sys_clk_freq)
# SATA PHY ---------------------------------------------------------------------------------
self.submodules.sata_phy = LiteSATAPHY(platform.device,
pads = platform.request("sata"),
gen = core_config["gen"],
clk_freq = sys_clk_freq,
data_width = 16,
with_csr = False)
self.comb += self.sata_phy.enable.eq(platform.request("enable"))
self.comb += platform.request("ready").eq(self.sata_phy.ready)
# SATA Core --------------------------------------------------------------------------------
self.submodules.sata_core = LiteSATACore(self.sata_phy)
# SATA Crossbar ----------------------------------------------------------------------------
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
# SATA User Ports --------------------------------------------------------------------------
for name, port in core_config["user_ports"].items():
# Native
if port["type"] == "native":
assert port["data_width"] == 32
user_port = self.sata_crossbar.get_port()
platform.add_extension(get_native_user_port_ios(name))
user_port_pads = platform.request("user_port_{}".format(name))
self.comb += [
user_port.sink.valid.eq(user_port_pads.sink_valid),
user_port.sink.last.eq(user_port_pads.sink_last),
user_port.sink.write.eq(user_port_pads.sink_write),
user_port.sink.read.eq(user_port_pads.sink_read),
user_port.sink.identify.eq(user_port_pads.sink_identify),
user_port.sink.sector.eq(user_port_pads.sink_sector),
user_port.sink.count.eq(user_port_pads.sink_count),
user_port_pads.sink_ready.eq(user_port.sink.ready),
]
self.comb += [
user_port_pads.source_valid.eq(user_port.source.valid),
user_port_pads.source_last.eq(user_port.source.last),
user_port_pads.source_write.eq(user_port.source.write),
user_port_pads.source_read.eq(user_port.source.read),
user_port_pads.source_identify.eq(user_port.source.identify),
user_port_pads.source_end.eq(user_port.source.end),
user_port_pads.source_failed.eq(user_port.source.failed),
user_port_pads.source_data.eq(user_port.source.data),
user_port.source.ready.eq(user_port_pads.source_ready),
]
else:
raise ValueError("Unsupported port type: {}".format(port["type"]))
# Timing constraints
platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/sata_clk_freq)
platform.add_period_constraint(self.sata_phy.crg.cd_sata_rx.clk, 1e9/sata_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.sata_phy.crg.cd_sata_tx.clk,
self.sata_phy.crg.cd_sata_rx.clk)
def __init__(self,
sys_clk_freq=int(150e6),
with_ethernet=False,
with_sata=False,
**kwargs):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on KC705",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# SATA (Experimental) ----------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litex.soc.interconnect import wishbone
from litesata.phy import LiteSATAPHY
from litesata.core import LiteSATACore
from litesata.frontend.arbitration import LiteSATACrossbar
from litesata.frontend.dma import LiteSATABlock2MemDMA
# IOs
_sata_io = [
# SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter
(
"sfp",
0,
Subsignal("txp", Pins("H2")),
Subsignal("txn", Pins("H1")),
Subsignal("rxp", Pins("G4")),
Subsignal("rxn", Pins("G3")),
),
]
platform.add_extension(_sata_io)
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
refclk=sata_refclk,
pads=platform.request("sfp"),
gen="gen1",
clk_freq=sys_clk_freq,
data_width=16)
# Core
self.submodules.sata_core = LiteSATACore(self.sata_phy)
# Crossbar
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
# Block2Mem DMA
bus = wishbone.Interface(data_width=32, adr_width=32)
self.submodules.sata_block2mem = LiteSATABlock2MemDMA(
user_port=self.sata_crossbar.get_port(),
bus=bus,
endianness=self.cpu.endianness)
self.bus.add_master("sata_block2mem", master=bus)
self.add_csr("sata_block2mem")
# Timing constraints
platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk,
1e9 / 75e6)
platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk,
1e9 / 75e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.sata_phy.crg.cd_sata_tx.clk,
self.sata_phy.crg.cd_sata_tx.clk)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
platform,
connector="fmc",
gen="gen3",
data_width=16,
with_analyzer=False):
assert connector in ["fmc", "sfp", "pcie"]
assert gen in ["gen1", "gen2", "gen3"]
sys_clk_freq = int(200e6)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(
self,
platform,
sys_clk_freq,
integrated_sram_size=0x1000,
ident="LiteSATA bench on KC705",
ident_version=True,
with_uart=True,
uart_name="bridge",
)
# SATA -------------------------------------------------------------------------------------
# RefClk
if connector == "fmc":
# Use 150MHz refclk provided by FMC.
sata_refclk = platform.request("fmc_refclk")
else:
# Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
refclk=sata_refclk,
pads=platform.request(connector),
gen=gen,
clk_freq=sys_clk_freq,
data_width=data_width)
# Core
self.submodules.sata_core = LiteSATACore(self.sata_phy)
# Crossbar
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
# BIST
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar,
with_csr=True)
self.add_csr("sata_bist")
# Block2Mem DMA
bus = wishbone.Interface(data_width=32, adr_width=32)
self.submodules.sata_block2mem = LiteSATABlock2MemDMA(
self.sata_crossbar.get_port(), bus)
self.bus.add_master("sata_block2mem", master=bus)
self.add_csr("sata_block2mem")
# Timing constraints
platform.add_period_constraint(
self.sata_phy.crg.cd_sata_tx.clk,
1e9 / 300e6 if data_width == 16 else 1e9 / 150e6)
platform.add_period_constraint(
self.sata_phy.crg.cd_sata_tx.clk,
1e9 / 300e6 if data_width == 16 else 1e9 / 150e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.sata_phy.crg.cd_sata_tx.clk,
self.sata_phy.crg.cd_sata_tx.clk)
# Leds -------------------------------------------------------------------------------------
# sys_clk
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led", 0).eq(sys_counter[26])
# tx_clk
tx_counter = Signal(32)
self.sync.sata_tx += tx_counter.eq(tx_counter + 1)
self.comb += platform.request("user_led", 1).eq(tx_counter[26])
# rx_clk
rx_counter = Signal(32)
self.sync.sata_rx += rx_counter.eq(rx_counter + 1)
self.comb += platform.request("user_led", 2).eq(rx_counter[26])
# ready
self.comb += platform.request("user_led",
3).eq(self.sata_phy.ctrl.ready)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
self.sata_phy.phy.tx_init.fsm,
self.sata_phy.phy.rx_init.fsm,
self.sata_phy.ctrl.fsm,
self.sata_phy.ctrl.ready,
self.sata_phy.source,
self.sata_phy.sink,
self.sata_core.command.sink,
self.sata_core.command.source,
self.sata_core.link.rx.fsm,
self.sata_core.link.tx.fsm,
self.sata_core.transport.rx.fsm,
self.sata_core.transport.tx.fsm,
self.sata_core.command.rx.fsm,
self.sata_core.command.tx.fsm,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 512, csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(self, platform, connector="fmc", gen="gen3",
with_global_analyzer = False,
with_sector2mem_analyzer = False,
with_mem2sector_analyzer = False):
assert connector in ["fmc", "sfp", "pcie"]
assert gen in ["gen1", "gen2", "gen3"]
sys_clk_freq = int(200e6)
sata_clk_freq = {"gen1": 75e6, "gen2": 150e6, "gen3": 300e6}[gen]
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, sys_clk_freq,
ident = "LiteSATA bench on KC705",
ident_version = True,
with_uart = True,
uart_name = "bridge")
# SATA -------------------------------------------------------------------------------------
# RefClk
sata_refclk = None
if connector != "fmc":
# Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(platform.device,
refclk = sata_refclk,
pads = platform.request(connector+"2sata"),
gen = gen,
clk_freq = sys_clk_freq,
data_width = 16)
self.add_csr("sata_phy")
# Core
self.submodules.sata_core = LiteSATACore(self.sata_phy)
# Crossbar
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
# BIST
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)
self.add_csr("sata_bist")
# Sector2Mem DMA
bus = wishbone.Interface(data_width=32, adr_width=32)
self.submodules.sata_sector2mem = LiteSATASector2MemDMA(self.sata_crossbar.get_port(), bus)
self.bus.add_master("sata_sector2mem", master=bus)
self.add_csr("sata_sector2mem")
# Mem2Sector DMA
bus = wishbone.Interface(data_width=32, adr_width=32)
self.submodules.sata_mem2sector = LiteSATAMem2SectorDMA(bus, self.sata_crossbar.get_port())
self.bus.add_master("sata_mem2sector", master=bus)
self.add_csr("sata_mem2sector")
# Timing constraints
platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/sata_clk_freq)
platform.add_period_constraint(self.sata_phy.crg.cd_sata_rx.clk, 1e9/sata_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.sata_phy.crg.cd_sata_tx.clk,
self.sata_phy.crg.cd_sata_rx.clk)
# Leds -------------------------------------------------------------------------------------
# sys_clk
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led", 0).eq(sys_counter[26])
# tx_clk
tx_counter = Signal(32)
self.sync.sata_tx += tx_counter.eq(tx_counter + 1)
self.comb += platform.request("user_led", 1).eq(tx_counter[26])
# rx_clk
rx_counter = Signal(32)
self.sync.sata_rx += rx_counter.eq(rx_counter + 1)
self.comb += platform.request("user_led", 2).eq(rx_counter[26])
# ready
self.comb += platform.request("user_led", 3).eq(self.sata_phy.ctrl.ready)
# Analyzers ---------------------------------------------------------------------------------
if with_global_analyzer:
analyzer_signals = [
self.sata_phy.phy.tx_init.fsm,
self.sata_phy.phy.rx_init.fsm,
self.sata_phy.ctrl.fsm,
self.sata_phy.ctrl.ready,
self.sata_phy.source,
self.sata_phy.sink,
self.sata_core.command.sink,
self.sata_core.command.source,
self.sata_core.link.rx.fsm,
self.sata_core.link.tx.fsm,
self.sata_core.transport.rx.fsm,
self.sata_core.transport.tx.fsm,
self.sata_core.command.rx.fsm,
self.sata_core.command.tx.fsm,
]
self.submodules.global_analyzer = LiteScopeAnalyzer(analyzer_signals, 512, csr_csv="global_analyzer.csv")
self.add_csr("global_analyzer")
if with_sector2mem_analyzer:
analyzer_signals = [
self.sata_sector2mem.start.re,
self.sata_sector2mem.fsm,
self.sata_sector2mem.port.sink,
self.sata_sector2mem.port.source,
self.sata_sector2mem.bus,
]
self.submodules.sector2mem_analyzer = LiteScopeAnalyzer(analyzer_signals, 2048, csr_csv="sector2mem_analyzer.csv")
self.add_csr("sector2mem_analyzer")
if with_mem2sector_analyzer:
analyzer_signals = [
self.sata_mem2sector.start.re,
self.sata_mem2sector.fsm,
self.sata_mem2sector.port.sink,
self.sata_mem2sector.port.source,
self.sata_mem2sector.bus,
]
self.submodules.mem2sector_analyzer = LiteScopeAnalyzer(analyzer_signals, 2048, csr_csv="mem2sector_analyzer.csv")
self.add_csr("mem2sector_analyzer")
def __init__(self, platform, revision="sata_gen3", trx_dw=16, nphys=4):
self.nphys = nphys
clk_freq = 200 * 1000000
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteSATA example design",
with_timer=False)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform)
# SATA PHYs
self.sata_phys = []
for i in range(self.nphys):
sata_phy = LiteSATAPHY(
platform.device,
platform.request("sata_clocks")
if i == 0 else self.sata_phys[0].crg.refclk,
platform.request("sata", i), revision, clk_freq, trx_dw)
sata_phy = ClockDomainsRenamer({
"sata_rx":
"sata_rx{}".format(str(i)),
"sata_tx":
"sata_tx{}".format(str(i))
})(sata_phy)
setattr(self.submodules, "sata_phy{}".format(str(i)), sata_phy)
self.sata_phys.append(sata_phy)
# SATA Cores
self.sata_cores = []
for i in range(self.nphys):
sata_core = LiteSATACore(self.sata_phys[i])
setattr(self.submodules, "sata_core{}".format(str(i)), sata_core)
self.sata_cores.append(sata_core)
# SATA Frontend
self.submodules.sata_mirroring = LiteSATAMirroring(self.sata_cores)
self.sata_crossbars = []
for i in range(self.nphys):
sata_crossbar = LiteSATACrossbar(self.sata_mirroring.ports[i])
setattr(self.submodules, "sata_crossbar{}".format(str(i)),
sata_crossbar)
self.sata_crossbars.append(sata_crossbar)
# SATA Application
self.sata_bists = []
for i in range(self.nphys):
sata_bist = LiteSATABIST(self.sata_crossbars[i], with_csr=True)
setattr(self.submodules, "sata_bist{}".format(str(i)), sata_bist)
self.sata_bists.append(sata_bist)
# Status Leds
self.submodules.status_leds = StatusLeds(platform, self.sata_phys)
platform.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk]
""")
for i in range(len(self.sata_phys)):
self.specials += [
Keep(ClockSignal("sata_rx{}".format(str(i)))),
Keep(ClockSignal("sata_tx{}".format(str(i))))
]
platform.add_platform_command("""
create_clock -name {sata_rx_clk} -period {sata_clk_period} [get_nets {sata_rx_clk}]
create_clock -name {sata_tx_clk} -period {sata_clk_period} [get_nets {sata_tx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}]
set_false_path -from [get_clocks {sata_rx_clk}] -to [get_clocks sys_clk]
set_false_path -from [get_clocks {sata_tx_clk}] -to [get_clocks sys_clk]
""".format(sata_rx_clk="sata_rx{}_clk".format(str(i)),
sata_tx_clk="sata_tx{}_clk".format(str(i)),
sata_clk_period="3.3" if trx_dw == 16 else "6.6"))
def __init__(self,
platform,
gen="gen2",
data_width=16,
with_analyzer=False):
assert gen in ["gen1", "gen2"]
sys_clk_freq = int(100e6)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
sys_clk_freq,
ident="LiteSATA bench on Nexys Video",
ident_version=True,
with_uart=True,
uart_name="bridge")
# SATA -------------------------------------------------------------------------------------
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
refclk=platform.request(
"fmc_refclk"), # Use 150MHz refclk provided by FMC.
pads=platform.request("fmc"),
gen=gen,
clk_freq=sys_clk_freq,
data_width=data_width)
# Core
self.submodules.sata_core = LiteSATACore(self.sata_phy)
# Crossbar
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
# BIST
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar,
with_csr=True)
self.add_csr("sata_bist")
# Timing constraints
platform.add_period_constraint(
self.sata_phy.crg.cd_sata_tx.clk,
1e9 / 150e6 if data_width == 16 else 1e9 / 75e6)
platform.add_period_constraint(
self.sata_phy.crg.cd_sata_tx.clk,
1e9 / 150e6 if data_width == 16 else 1e9 / 75e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.sata_phy.crg.cd_sata_tx.clk,
self.sata_phy.crg.cd_sata_tx.clk)
# Leds -------------------------------------------------------------------------------------
# sys_clk
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led", 0).eq(sys_counter[26])
# tx_clk
tx_counter = Signal(32)
self.sync.sata_tx += tx_counter.eq(tx_counter + 1)
self.comb += platform.request("user_led", 1).eq(tx_counter[26])
# rx_clk
rx_counter = Signal(32)
self.sync.sata_rx += rx_counter.eq(rx_counter + 1)
self.comb += platform.request("user_led", 2).eq(rx_counter[26])
# ready
self.comb += platform.request("user_led",
3).eq(self.sata_phy.ctrl.ready)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
self.sata_phy.phy.tx_init.fsm,
self.sata_phy.phy.rx_init.fsm,
self.sata_phy.ctrl.fsm,
self.sata_phy.ctrl.ready,
self.sata_phy.source,
self.sata_phy.sink,
self.sata_core.command.sink,
self.sata_core.command.source,
self.sata_core.link.rx.fsm,
self.sata_core.link.tx.fsm,
self.sata_core.transport.rx.fsm,
self.sata_core.transport.tx.fsm,
self.sata_core.command.rx.fsm,
self.sata_core.command.tx.fsm,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 512, csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(self, platform, port=0, gen="gen2", with_analyzer=False):
assert gen in ["gen1", "gen2"]
sys_clk_freq = int(100e6)
sata_clk_freq = {"gen1": 75e6, "gen2": 150e6}[gen]
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
sys_clk_freq,
ident="LiteSATA bench on Axiom Beta SATA",
ident_version=True)
# JTAGBone ---------------------------------------------------------------------------------
self.add_jtagbone()
# SATA -------------------------------------------------------------------------------------
# PHY
self.submodules.sata_phy = LiteSATAPHY(platform.device,
pads=platform.request(
"sata", port),
gen=gen,
clk_freq=sys_clk_freq,
data_width=16)
self.add_csr("sata_phy")
# Core
self.submodules.sata_core = LiteSATACore(self.sata_phy)
# Crossbar
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
# BIST
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar,
with_csr=True)
self.add_csr("sata_bist")
# Timing constraints
platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk,
1e9 / sata_clk_freq)
platform.add_period_constraint(self.sata_phy.crg.cd_sata_rx.clk,
1e9 / sata_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.sata_phy.crg.cd_sata_tx.clk,
self.sata_phy.crg.cd_sata_rx.clk)
# Leds -------------------------------------------------------------------------------------
# sys_clk
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led_n", 0).eq(~sys_counter[26])
# tx_clk
tx_counter = Signal(32)
self.sync.sata_tx += tx_counter.eq(tx_counter + 1)
self.comb += platform.request("user_led_n", 1).eq(~tx_counter[26])
# rx_clk
rx_counter = Signal(32)
self.sync.sata_rx += rx_counter.eq(rx_counter + 1)
self.comb += platform.request("user_led_n", 2).eq(~rx_counter[26])
# ready
self.comb += platform.request("module_led").eq(
self.sata_phy.ctrl.ready)
self.comb += platform.request("user_led_n",
3).eq(~self.sata_phy.ctrl.ready)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
self.sata_phy.phy.tx_init.fsm,
self.sata_phy.phy.rx_init.fsm,
self.sata_phy.ctrl.fsm,
self.sata_phy.ctrl.ready,
self.sata_phy.source,
self.sata_phy.sink,
self.sata_core.command.sink,
self.sata_core.command.source,
self.sata_core.link.rx.fsm,
self.sata_core.link.tx.fsm,
self.sata_core.transport.rx.fsm,
self.sata_core.transport.tx.fsm,
self.sata_core.command.rx.fsm,
self.sata_core.command.tx.fsm,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 512, csr_csv="analyzer.csv")
self.add_csr("analyzer")
