def make_soc(self, **kwargs) -> litex_soc.LiteXSoC:
soc = super().make_soc(integrated_rom_size=0,
integrated_rom_init=[],
**kwargs)
soc.spiflash_region = SoCRegion(0x00000000,
16 * MB,
mode="r",
cached=True,
linker=True)
soc.submodules.spiflash_phy = LiteSPIPHY(
soc.platform.request("spiflash"),
MX25L12835F(Codes.READ_1_1_1),
default_divisor=1)
soc.submodules.spiflash_mmap = LiteSPI(
phy=soc.spiflash_phy,
clk_freq=soc.sys_clk_freq,
mmap_endianness=soc.cpu.endianness)
soc.csr.add("spiflash_mmap")
soc.csr.add("spiflash_phy")
soc.bus.add_slave(name="spiflash",
slave=soc.spiflash_mmap.bus,
region=soc.spiflash_region)
soc.bus.add_region("rom", soc.spiflash_region)
return soc
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
with_spi_xip=False,
**kwargs):
platform = netv2.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=K4B2G1646F(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# SPI XIP ----------------------------------------------------------------------------------
if with_spi_xip:
from litespi import LiteSPI
from litespi.phy.generic import LiteSPIPHY
spi_xip_size = 1024 * 1024 * 8
self.submodules.spiphy = LiteSPIPHY(platform.request("spiflash4x"))
self.submodules.spictl = LiteSPI(phy=self.spiphy,
endianness=self.cpu.endianness)
spi_xip_region = SoCRegion(origin=self.mem_map.get("spixip", None),
size=spi_xip_size,
cached=False)
self.bus.add_slave(name="spixip",
slave=self.spictl.bus,
region=spi_xip_region)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def setup_litespi_flash(self):
self.submodules.spiflash_phy = LiteSPIPHY(
self.platform.request("spiflash4x"),
GD25LQ128D(Codes.READ_1_1_4),
default_divisor=0,
rate='1:2',
extra_latency=1)
self.submodules.spiflash_mmap = LiteSPI(
phy=self.spiflash_phy, mmap_endianness=self.cpu.endianness)
self.csr.add("spiflash_mmap")
self.csr.add("spiflash_phy")
self.bus.add_slave(name="spiflash",
slave=self.spiflash_mmap.bus,
region=self.spiflash_region)
def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, ident_version=True, with_jtagbone=True, with_mapped_flash=False, **kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Arty A7",
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_mapped_flash)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Flash (through LiteSPI, experimental).
if with_mapped_flash:
self.submodules.spiflash_phy = LiteSPIPHY(platform.request("spiflash4x"), S25FL128L(Codes.READ_1_1_4))
self.submodules.spiflash_mmap = LiteSPI(self.spiflash_phy, clk_freq=sys_clk_freq, mmap_endianness=self.cpu.endianness)
spiflash_region = SoCRegion(origin=self.mem_map.get("spiflash", None), size=S25FL128L.total_size, cached=False)
self.bus.add_slave(name="spiflash", slave=self.spiflash_mmap.bus, region=spiflash_region)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_daughterboard=False,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
ident_version=True, with_jtagbone=True, with_mapped_flash=False, **kwargs):
platform = qmtech_xc7a35t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on QMTech XC7A35T" + (" + Daughterboard" if with_daughterboard else ""),
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet or with_etherbone, with_video_terminal or with_video_framebuffer)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# The daughterboard has the tx clock wired to a non-clock pin, so we can't help it
self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]")
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Flash (through LiteSPI, experimental).
if with_mapped_flash:
self.submodules.spiflash_phy = LiteSPIPHY(platform.request("spiflash4x"), MT25QL128(Codes.READ_1_1_1))
self.submodules.spiflash_mmap = LiteSPI(self.spiflash_phy, clk_freq=sys_clk_freq, mmap_endianness=self.cpu.endianness)
spiflash_region = SoCRegion(origin=self.mem_map.get("spiflash", None), size=MT25QL128.total_size, cached=False)
self.bus.add_slave(name="spiflash", slave=self.spiflash_mmap.bus, region=spiflash_region)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
if not with_daughterboard and kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "jtag_serial"
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
with_spiflash=False,
**kwargs):
platform = arty.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
interface_type="MEMORY")
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# SPIFlash ---------------------------------------------------------------------------------
if with_spiflash:
self.submodules.spiflash_phy = LiteSPIPHY(
platform.request("spiflash"), S25FL128S(Codes.READ_1_1_1))
self.submodules.spiflash_mmap = LiteSPI(
phy=self.spiflash_phy,
clk_freq=sys_clk_freq,
mmap_endianness=self.cpu.endianness)
self.add_csr("spiflash_mmap")
self.add_csr("spiflash_phy")
spiflash_size = 1024 * 1024 * 16
spiflash_region = SoCRegion(origin=self.mem_map.get(
"spiflash", None),
size=spiflash_size,
cached=False)
self.bus.add_slave(name="spiflash",
slave=self.spiflash_mmap.bus,
region=spiflash_region)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
def __init__(self,
with_sdram=False,
with_spi_xip=False,
with_ethernet=False,
with_etherbone=False,
etherbone_mac_address=0x10e2d5000001,
etherbone_ip_address="192.168.1.51",
with_analyzer=False,
sdram_module="MT48LC16M16",
sdram_init=[],
sdram_data_width=32,
sdram_verbosity=0,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteX Simulation",
ident_version=True,
l2_reverse=False,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# SPI XIP ----------------------------------------------------------------------------------
if with_spi_xip:
spi_xip_size = kwargs["spi_xip_size"]
self.submodules.spiphy = LiteSPIPHYModel(
spi_xip_size, init=kwargs["spi_xip_init"])
self.submodules.spictl = LiteSPI(phy=self.spiphy,
endianness=self.cpu.endianness)
spi_xip_region = SoCRegion(origin=self.mem_map.get("spixip", None),
size=spi_xip_size,
cached=False)
self.bus.add_slave(name="spixip",
slave=self.spictl.bus,
region=spi_xip_region)
# SDRAM ------------------------------------------------------------------------------------
if with_sdram:
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
sdram_module_cls = getattr(litedram_modules, sdram_module)
sdram_rate = "1:{}".format(
sdram_module_nphases[sdram_module_cls.memtype])
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
phy_settings = get_sdram_phy_settings(memtype=sdram_module.memtype,
data_width=sdram_data_width,
clk_freq=sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module,
settings=phy_settings,
clk_freq=sdram_clk_freq,
verbosity=sdram_verbosity,
init=sdram_init)
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# Reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024)
#assert not (with_ethernet and with_etherbone)
if with_ethernet and with_etherbone:
dw = 8
etherbone_ip_address = convert_ip(etherbone_ip_address)
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0))
self.add_csr("ethphy")
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=dw,
interface="hybrid",
endianness=self.cpu.endianness,
hw_mac=etherbone_mac_address)
# SoftCPU
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin,
self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# HW ethernet
self.submodules.arp = LiteEthARP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
sys_clk_freq,
dw=dw)
self.submodules.ip = LiteEthIP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
self.arp.table,
dw=dw)
self.submodules.icmp = LiteEthICMP(self.ip,
etherbone_ip_address,
dw=dw)
self.submodules.udp = LiteEthUDP(self.ip,
etherbone_ip_address,
dw=dw)
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Ethernet ---------------------------------------------------------------------------------
elif with_ethernet:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0))
self.add_csr("ethphy")
# Ethernet MAC
ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
if with_etherbone:
ethmac = ClockDomainsRenamer({
"eth_tx": "ethphy_eth_tx",
"eth_rx": "ethphy_eth_rx"
})(ethmac)
self.submodules.ethmac = ethmac
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin,
self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# Etherbone --------------------------------------------------------------------------------
elif with_etherbone:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0)) # FIXME
self.add_csr("ethphy")
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
mac_address=etherbone_mac_address,
ip_address=etherbone_ip_address,
clk_freq=sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [self.cpu.ibus, self.cpu.dbus]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
self.add_csr("analyzer")
def __init__(self,
sys_clk_freq=int(60e6),
with_ethernet=False,
with_etherbone=False,
with_spiflash=False,
ip_address=None,
mac_address=None,
**kwargs):
platform = colorlight_5a_75e.Platform()
platform.add_extension(ios)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteX LiteSPI SoC",
ident_version=True,
csr_data_width=32,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_rst=(kwargs["uart_name"] != "serial"))
# SDRAM ------------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=M12L16161A(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# SPIFlash ---------------------------------------------------------------------------------
if with_spiflash:
flash = W25Q32JV(Codes.READ_1_1_1)
self.submodules.spiflash_phy = LiteSPIPHY(
pads=platform.request("spiflash"),
flash=flash,
device=platform.device)
self.submodules.spiflash_mmap = LiteSPI(
phy=self.spiflash_phy,
clk_freq=sys_clk_freq,
mmap_endianness=self.cpu.endianness)
self.add_csr("spiflash_mmap")
self.add_csr("spiflash_phy")
spiflash_region = SoCRegion(origin=self.mem_map.get(
"spiflash", None),
size=flash.total_size,
cached=False)
self.bus.add_slave(name="spiflash",
slave=self.spiflash_mmap.bus,
region=spiflash_region)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address)
def __init__(self,
variant="a7-35",
toolchain="vivado",
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
ident_version=True,
with_jtagbone=True,
with_mapped_flash=False,
**kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
kwargs["cpu_type"] = "vexriscv_smp"
kwargs["cpu_variant"] = "linux"
kwargs["cpu_cls"] = VexRiscvSMP
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
ident_version=ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_mapped_flash)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Flash (through LiteSPI, experimental).
if with_mapped_flash:
self.submodules.spiflash_phy = LiteSPIPHY(
platform.request("spiflash4x"), S25FL128L(Codes.READ_1_1_4))
self.submodules.spiflash_mmap = LiteSPI(
self.spiflash_phy,
clk_freq=sys_clk_freq,
mmap_endianness=self.cpu.endianness)
spiflash_region = SoCRegion(origin=self.mem_map.get(
"spiflash", None),
size=S25FL128L.total_size,
cached=False)
self.bus.add_slave(name="spiflash",
slave=self.spiflash_mmap.bus,
region=spiflash_region)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# USB Host ---------------------------------------------------------------------------------
from litex.soc.cores.usb_ohci import USBOHCI
from litex.build.generic_platform import Subsignal, Pins, IOStandard
_usb_pmod_ios = [(
"usb_pmoda",
0,
Subsignal("dp", Pins("pmoda:0")),
Subsignal("dm", Pins("pmoda:4")),
IOStandard("LVCMOS33"),
)]
platform.add_extension(_usb_pmod_ios)
self.submodules.usb_ohci = USBOHCI(platform,
platform.request("usb_pmoda"),
usb_clk_freq=int(48e6))
self.bus.add_slave("usb_ohci_ctrl",
self.usb_ohci.wb_ctrl,
region=SoCRegion(origin=self.mem_map["usb_ohci"],
size=0x100000,
cached=False)) # FIXME: Mapping.
self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)