def __init__(self, bios_flash_offset, **kwargs):
sys_clk_freq = int(24e6)
platform = icebreaker.Platform()
# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
# Set CPU variant / reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
self.submodules.spram = Up5kSPRAM(size=64*kB)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, 64*kB)
# SPI Flash --------------------------------------------------------------------------------
self.submodules.spiflash = SpiFlash(platform.request("spiflash4x"), dummy=6, endianness="little")
self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=16*mB)
self.add_csr("spiflash")
# Add ROM linker region --------------------------------------------------------------------
self.add_memory_region("rom", self.mem_map["spiflash"] + bios_flash_offset, 32*kB, type="cached+linker")
# Leds -------------------------------------------------------------------------------------
counter = Signal(32)
self.sync += counter.eq(counter + 1)
self.comb += platform.request("user_ledr_n").eq(counter[26])
self.comb += platform.request("user_ledg_n").eq(~counter[26])
def __init__(self, bios_flash_offset, **kwargs):
sys_clk_freq = int(24e6)
platform = icebreaker.Platform()
platform.add_extension(icebreaker.break_off_pmod)
# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
# Set CPU variant / reset address
kwargs[
"cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on iCEBreaker",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
self.submodules.spram = Up5kSPRAM(size=128 * kB)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128 * kB))
# SPI Flash --------------------------------------------------------------------------------
self.add_spi_flash(mode="1x", dummy_cycles=8)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region(
"rom",
SoCRegion(origin=self.mem_map["spiflash"] + bios_flash_offset,
size=32 * kB,
linker=True))
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")