def main(): description = "LiteX-VexRiscv SoC Builder\n\n" parser = argparse.ArgumentParser( description=description, formatter_class=argparse.RawTextHelpFormatter) parser.add_argument("--build", action="store_true", help="build bitstream") parser.add_argument("--load", action="store_true", help="load bitstream (to SRAM)") parser.add_argument("--flash", action="store_true", help="flash bitstream/images (to SPI Flash)") args = parser.parse_args() if args.build: platform = basys3.Platform() dut = System(platform) platform.build(dut, build_dir="build/sys_accel_simulator_release/gateware") if args.load: from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() prog.load_bitstream( "build/sys_accel_simulator_release/gateware/top.bit") if args.flash: from litex.build.openocd import OpenOCD prog = OpenOCD("../prog/openocd_xilinx.cfg", flash_proxy_basename="../prog/bscan_spi_xc7a35t.bit") prog.set_flash_proxy_dir(".") prog.flash(0, "build/sys_accel_simulator_release/gateware/top.bin")
def flash(): from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer(flash_part="mt25ql256-spi-x1_x2_x4") prog.flash(0, "build/gateware/ac701.mcs") exit()