예제 #1
0
파일: tofe.py 프로젝트: xobs/lxsocsupport
    def __init__(self, platform, shared_uart):
        TOFE.__init__(self, platform)

        # UARTs
        shared_uart.add_uart_pads(platform.request('tofe_lsio_serial'))
        shared_uart.add_uart_pads(platform.request('tofe_lsio_pmod_serial'))

        # LEDs
        lsio_leds = Signal(4)
        self.submodules.lsio_leds = GPIOOut(lsio_leds)
        self.comb += [
            platform.request('tofe_lsio_user_led', 0).eq(lsio_leds[0]),
            platform.request('tofe_lsio_user_led', 1).eq(lsio_leds[1]),
            platform.request('tofe_lsio_user_led', 2).eq(lsio_leds[2]),
            platform.request('tofe_lsio_user_led', 3).eq(lsio_leds[3]),
        ]
        # Switches
        lsio_sws = Signal(4)
        self.submodules.lsio_sws = GPIOIn(lsio_sws)
        self.comb += [
            lsio_sws[0].eq(~platform.request('tofe_lsio_user_sw', 0)),
            lsio_sws[1].eq(~platform.request('tofe_lsio_user_sw', 1)),
            lsio_sws[2].eq(~platform.request('tofe_lsio_user_sw', 2)),
            lsio_sws[3].eq(~platform.request('tofe_lsio_user_sw', 3)),
        ]
    def __init__(self, sys_clk_freq, output_dir, *args, **kwargs):
        self._logger = logging.getLogger("ZephyrSoC")

        super().__init__(
            cpu_type="vexriscv",
            cpu_variant="full",
            csr_data_width=8,
            integrated_rom_size=0x8000,
            *args,
            **kwargs,
        )  # TODO: Test if we actually need "full" for ecall

        self.submodules.gpio_leds = GPIOOut(self.platform.request("gpio_leds"))
        self.add_csr("gpio_leds")

        self.submodules.switches = GPIOIn(self.platform.request_all("sw"))
        self.add_csr("switches")

        self.platform.add_extension(pmod1_uart_ios)
        self.add_uartbone(name="pmod1_uart")

        analyzer_signals = [self.cpu.ibus, self.cpu.dbus]
        self.submodules.analyzer = LiteScopeAnalyzer(
            analyzer_signals,
            depth=512,
            clock_domain="sys",
            csr_csv=os.path.join(output_dir, "analyzer.csv"),
        )
예제 #3
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    def __init__(self, platform, clk_freq):
        switches = Signal(1)
        leds = Signal(2)

        self.reset = Signal()

        # # #

        self.submodules.switches = GPIOIn(switches)
        self.submodules.leds = GPIOOut(leds)
        self.comb += [
           switches[0].eq(~platform.request("pwrsw")),
           platform.request("hdled").eq(~leds[0]),
           platform.request("pwled").eq(~leds[1]),
        ]

        # generate a reset when power switch is pressed for 1 second
        self.submodules.reset_timer = WaitTimer(clk_freq)
        self.comb += [
            self.reset_timer.wait.eq(switches[0]),
            self.reset.eq(self.reset_timer.done)
        ]
예제 #4
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    def __init__(self, platform, clk_freq):

        # Work out how many LEDs this board has
        user_leds = []
        while True:
            try:
                user_leds.append(platform.request("user_led", len(user_leds)))
            except ConstraintError:
                break

        rgb_leds = []
        while True:
            try:
                rgb_leds.append(platform.request("rgb_led", len(rgb_leds)))
            except ConstraintError:
                break
        for rgb in rgb_leds:
            # TODO: Common anode only for now. Support common cathode.
            r_n = Signal()
            g_n = Signal()
            b_n = Signal()

            self.comb += [
                rgb.r.eq(~r_n),
                rgb.g.eq(~g_n),
                rgb.b.eq(~b_n),
            ]

            user_leds.extend([r_n, g_n, b_n])

        if user_leds:
            leds = Signal(len(user_leds))
            self.submodules.leds = GPIOOut(leds)
            for i in range(0, len(user_leds)):
                self.comb += [
                    user_leds[i].eq(leds[i]),
                ]
        self._leds_count = CSRConstant(len(user_leds))

        # Work out how many switches this board has
        user_sws = []
        while True:
            try:
                user_sws.append(platform.request("user_sw", len(user_sws)))
            except ConstraintError:
                break

        if user_sws:
            switches = Signal(len(user_sws))
            self.submodules.switches = GPIOIn(switches)
            for i in range(0, len(user_sws)):
                self.comb += [
                    switches[i].eq(~user_sws[i]),
                ]
        self._switches_count = CSRConstant(len(user_sws))

        # Work out how many push buttons this board has
        user_btns = []
        while True:
            try:
                user_btns.append(platform.request("user_btn", len(user_btns)))
            except ConstraintError:
                break

        if user_btns:
            self.submodules.buttons_ev = EventManager()

            _10ms = int(clk_freq * (10e-3))

            for i in range(0, len(user_btns)):
                btn_ev = EventSourceProcess()
                btn_timer = WaitTimer(_10ms)

                setattr(self.buttons_ev, "btn_ev{}".format(i), btn_ev)

                self.comb += [
                    btn_timer.wait.eq(user_btns[i]),
                    btn_ev.trigger.eq(~btn_timer.done),
                ]

                self.submodules += [btn_timer]

            self.buttons_ev.finalize()
        self._buttons_count = CSRConstant(len(user_btns))
예제 #5
0
    def __init__(self, 
            variant="a7-35",
            toolchain="vivado",
            sys_clk_freq=int(100e6),
            with_ethernet=False,
            with_etherbone=False,
            eth_ip="192.168.1.50",
            eth_dynamic_ip=False,
            ident_version=True,
            analyzer_csv="analyzer.csv",
            **kwargs):
        platform = arty.Platform(variant=variant, toolchain=toolchain)
        kwargs["integrated_rom_size"] = 0x10000 if with_etherbone else 0x8000

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident          = "LiteX SoC on Arty A7",
            ident_version  = ident_version,
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
                memtype        = "DDR3",
                nphases        = 4,
                sys_clk_freq   = sys_clk_freq)
            self.add_csr("ddrphy")
            self.add_sdram("sdram",
                phy                     = self.ddrphy,
                module                  = MT41K128M16(sys_clk_freq, "1:4"),
                origin                  = self.mem_map["main_ram"],
                size                    = kwargs.get("max_sdram_size", 0x40000000),
                l2_cache_size           = kwargs.get("l2_size", 8192),
                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                l2_cache_reverse        = True
            )

        # Ethernet / Etherbone ---------------------------------------------------------------------
        if with_ethernet or with_etherbone:
            self.submodules.ethphy = LiteEthPHYMII(
                clock_pads = self.platform.request("eth_clocks"),
                pads       = self.platform.request("eth"))
            self.add_csr("ethphy")
            if with_ethernet:
                self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
            if with_etherbone:
                self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)

        _dws1000_ardu_io = [
            ("dw1000_spi", 0,
                Subsignal("clk",  Pins("ck_io:ck_io13")),
                Subsignal("mosi", Pins("ck_io:ck_io11")),
                Subsignal("cs_n", Pins("ck_io:ck_io10")),
                Subsignal("miso", Pins("ck_io:ck_io12")),
                Subsignal("pha", Pins("ck_io:ck_io0"), Misc("PULLDOWN True")),
                Subsignal("pol", Pins("ck_io:ck_io1"), Misc("PULLDOWN True")),
                Misc("SLEW=FAST"),
                IOStandard("LVCMOS33"),
            ),
            ("dw1000_led", 0, Pins("ck_io:ck_io3"),  IOStandard("LVCMOS33")), # TX LED on the DWS1000 module
            ("dw1000_led", 1, Pins("ck_io:ck_io4"),  IOStandard("LVCMOS33")), # RX LED on the DWS1000 module
            ("dw1000_info", 0,
                Subsignal("exton",   Pins("ck_io:ck_a0")),
                Subsignal("wakeup",   Pins("ck_io:ck_io9")),
                Subsignal("irq",   Pins("ck_io:ck_io8")),
                IOStandard("LVCMOS33"),
            ),
            ("dw1000_rstn", 0,
                Pins("ck_io:ck_io7"),
                IOStandard("LVCMOS33"),
            ),
        ]
        platform.add_extension(_dws1000_ardu_io)
        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
            pads         = platform.request_all("dw1000_led"),
            sys_clk_freq = sys_clk_freq)
        self.add_csr("leds")

        self.submodules.dw1000_rstn = GPIOTristate(platform.request("dw1000_rstn", 0))
        self.add_csr("dw1000_rstn")

        self.submodules.dw1000_info = GPIOIn(platform.request("dw1000_info"))
        self.add_csr("dw1000_info")

        # SPI with LiteScope
        self.add_spi_master()
        print(dir(self.cpu.ibus))
        analyzer_signals = [
            self.spi_master._control.storage,
            self.spi_master._status.status,
            self.spi_master._cs.storage,
            self.spi_master.mosi,
            self.spi_master.miso,
            self.spi_master.pads.clk,
            self.spi_master.pads.cs_n,
            self.spi_master.pads.mosi,
            self.spi_master.pads.miso,
            self.dw1000_rstn._oe.storage,
            self.dw1000_rstn._in.status,
            self.dw1000_rstn._out.storage,
            self.dw1000_info._in.status,
            self.cpu.ibus.adr,
            self.cpu.ibus.stb,
            self.cpu.ibus.dat_w,
            self.cpu.ibus.dat_r

        ]
        self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
            depth=1024,
            clock_domain="sys",
            csr_csv=analyzer_csv
        )
        self.add_csr("analyzer")
 def add_switches(self):
     self.submodules.switches = GPIOIn(Cat(platform_request_all(self.platform, "user_sw")))
     self.add_csr("switches")
예제 #7
0
 def add_switches(self):
     self.submodules.switches = GPIOIn(Cat(
         self.platform.request_all("user_sw")),
                                       with_irq=True)
     self.add_interrupt("switches")
예제 #8
0
 def __init__(self, **kwargs):
     EthernetSoC.__init__(self, **kwargs)
     self.set_bios_ip("192.168.0.55", "192.168.0.45")
     # flash-rom
     self.add_constant("FLASH_BOOT_ADDRESS",
                       self.mem_map["spiflash"] + FLASH_BOOTROM_OFFSET)
     self.submodules.spiflash = SpiFlash(
         self.platform.request("spiflash4x"),
         dummy=6,  # see datasheet for dummy cycles
         div=2,  # multiple of 2
         with_bitbang=True,
         endianness=self.cpu.endianness,
         addr32bit=True)
     self.spiflash.add_clk_primitive(self.platform.device)
     self.add_memory_region("spiflash",
                            self.mem_map["spiflash"],
                            self.flash_size,
                            type="io")
     self.add_wb_slave(self.mem_map["spiflash"],
                       self.spiflash.bus,
                       size=self.flash_size)
     self.add_csr("spiflash")
     if self.full_board:
         if self.fast_sd:
             self.submodules.sdmmc = SDCard(self.platform, "sdmmc")
             self.add_wb_master(self.sdmmc.master_bus)
             self.add_memory_region("sdmmc",
                                    self.mem_map["sdmmc"],
                                    self.sdmmc.get_size(),
                                    type="io")
             self.add_wb_slave(self.mem_map["sdmmc"],
                               self.sdmmc.slave_bus,
                               size=self.sdmmc.get_size())
             self.sdmmc_cmd_irq = self.sdmmc.cmd_irq
             self.sdmmc_dat_irq = self.sdmmc.dat_irq
             self.add_interrupt("sdmmc_cmd_irq")
             self.add_interrupt("sdmmc_dat_irq")
         else:
             # SPI0: sd-card
             self.submodules.spi0 = SPIMaster(self.platform,
                                              name="sdspi",
                                              busmaster=False)
             if hasattr(self.spi0, "master_bus"):
                 self.add_wb_master(self.spi0.master_bus)
             self.add_memory_region("spi0",
                                    self.mem_map["spi0"],
                                    self.spi0.get_size(),
                                    type="io")
             self.add_wb_slave(self.mem_map["spi0"],
                               self.spi0.slave_bus,
                               size=self.spi0.get_size())
             self.add_csr("spi0")
             self.add_interrupt("spi0")
         sd_reset = self.platform.request("sd_reset")
         sd_cd = self.platform.request("sd_cd")
         self.comb += sd_reset.eq(0)
         # SPI1: waveshare35a
         self.submodules.spi1 = SPIMaster(self.platform,
                                          name="ws35a_spi",
                                          cs_width=2,
                                          busmaster=False)
         if hasattr(self.spi1, "master_bus"):
             self.add_wb_master((self.spi1.master_bus))
         self.add_memory_region("spi1",
                                self.mem_map["spi1"],
                                self.spi1.get_size(),
                                type="io")
         self.add_wb_slave(self.mem_map["spi1"],
                           self.spi1.slave_bus,
                           size=self.spi1.get_size())
         self.add_csr("spi1")
         self.add_interrupt("spi1")
         # waveshare35a
         ws35a_rs = self.platform.request("ws35a_rs")
         ws35a_reset = self.platform.request("ws35a_reset")
         ws35a_pendown = self.platform.request("ws35a_int")
         self.submodules.ws35a = TouchscreenInterrupt(ws35a_pendown)
         self.add_interrupt("ws35a")
         # gpio0: leds, ws35a controls
         board_led = Signal()
         self.comb += self.platform.request("board_led").eq(~board_led)
         gpio0_signals = Cat(
             self.platform.request("user_led", 0),
             self.platform.request("user_led", 1),
             self.platform.request("user_led", 2),
             self.platform.request("user_led", 3),
             board_led,
             self.reset,
             ws35a_rs,
             ws35a_reset,
         )
         self.submodules.gpio0 = GPIOOut(gpio0_signals)
         self.add_csr("gpio0")
         # gpio1: touchscreen pendown, sd-card-detect
         gpio1_signals = Cat(ws35a_pendown, sd_cd)
         self.submodules.gpio1 = GPIOIn(gpio1_signals)
         self.add_csr("gpio1")
         # timer1
         self.submodules.timer1 = Timer()
         self.add_csr("timer1")
         self.add_interrupt("timer1")
         # AES
         self.submodules.aes = AES(self.platform)
         self.add_memory_region("aes",
                                self.mem_map["aes"],
                                self.aes.get_size(),
                                type="io")
         self.add_wb_slave(self.mem_map["aes"],
                           self.aes.bus,
                           size=self.aes.get_size())
         # SHA1
         self.submodules.sha1 = SHA1(self.platform)
         self.add_memory_region("sha1",
                                self.mem_map["sha1"],
                                self.sha1.get_size(),
                                type="io")
         self.add_wb_slave(self.mem_map["sha1"],
                           self.sha1.bus,
                           size=self.sha1.get_size())
         # memirq channels
         # channel 0
         self.submodules.to_sel4_master0 = MemIrq()
         self.add_csr("to_sel4_master0")
         self.add_interrupt("to_sel4_master0")
         self.submodules.to_sel4_slave0 = MemIrq()
         self.add_csr("to_sel4_slave0")
         self.add_interrupt("to_sel4_slave0")
         self.submodules.to_linux_master0 = MemIrq()
         self.add_csr("to_linux_master0")
         self.add_interrupt("to_linux_master0")
         self.submodules.to_linux_slave0 = MemIrq()
         self.add_csr("to_linux_slave0")
         self.add_interrupt("to_linux_slave0")
         # channel 1
         self.submodules.to_sel4_master1 = MemIrq()
         self.add_csr("to_sel4_master1")
         self.add_interrupt("to_sel4_master1")
         self.submodules.to_sel4_slave1 = MemIrq()
         self.add_csr("to_sel4_slave1")
         self.add_interrupt("to_sel4_slave1")
         self.submodules.to_linux_master1 = MemIrq()
         self.add_csr("to_linux_master1")
         self.add_interrupt("to_linux_master1")
         self.submodules.to_linux_slave1 = MemIrq()
         self.add_csr("to_linux_slave1")
         self.add_interrupt("to_linux_slave1")
         # dma test
         self.submodules.dmatest = DMATest()
         self.add_wb_master(self.dmatest.master_bus)
         self.add_csr("dmatest")
     self.dts = None
예제 #9
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    def __init__(self, sys_clk_freq=int(200e6), disable_sdram=False, **kwargs):
        platform = ted_tfoil.Platform()

        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on tfoil",
                         ident_version=True,
                         **kwargs)

        self.submodules.crg = _CRG(platform, sys_clk_freq)

        if not disable_sdram:
            if not self.integrated_main_ram_size:
                self.submodules.ddrphy = usddrphy.USPDDRPHY(
                    platform.request("ddram"),
                    memtype="DDR4",
                    sys_clk_freq=sys_clk_freq,
                    iodelay_clk_freq=400e6)
                self.add_sdram("sdram",
                               phy=self.ddrphy,
                               module=MT40A1G8(sys_clk_freq, "1:4"),
                               size=0x40000000,
                               l2_cache_size=kwargs.get("l2_size", 8192))

        self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
                                         sys_clk_freq=sys_clk_freq)

        i2c_master_pads = [
            platform.request("i2c_tca9555", 0),
            platform.request("i2c_tca9555", 1),
            platform.request("i2c_tca9555", 2),
            platform.request("i2c_tca9555", 3),
            platform.request("i2c_tca9555", 4),
            platform.request("i2c_tca9555", 5),
            platform.request("i2c_tca9555", 6),
            platform.request("i2c_tca9548", 0),
            platform.request("i2c_tca9548", 1),
            platform.request("i2c_tca9548", 2),
            platform.request("i2c_tca9548", 3),
            platform.request("i2c_si5341", 0),
            platform.request("i2c_si5341", 1),
        ]

        self.submodules.i2c = I2CMasterMP(platform, i2c_master_pads)

        self.submodules.sb_tca9548 = GPIOOut(
            pads=platform.request_all("tca9548_reset_n"))

        sb_si5341_o_pads = Cat([
            platform.request("si5341_in_sel_0", 0),
            platform.request("si5341_in_sel_0", 1),
            platform.request("si5341_syncb", 0),
            platform.request("si5341_syncb", 1),
            platform.request("si5341_rstb", 0),
            platform.request("si5341_rstb", 1),
        ])
        sb_si5341_i_pads = Cat([
            platform.request("si5341_lolb", 0),
            platform.request("si5341_lolb", 1),
        ])
        self.submodules.sb_si5341_o = GPIOOut(pads=sb_si5341_o_pads)
        self.submodules.sb_si5341_i = GPIOIn(pads=sb_si5341_i_pads)

        self._add_aurora(platform)
예제 #10
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    def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs):
        # Board Revision ---------------------------------------------------------------------------
        revision = kwargs.get("revision", "0.2")
        device = kwargs.get("device", "25F")

        platform = orangecrab.Platform(revision=revision,
                                       device=device,
                                       toolchain=toolchain)

        platform.add_extension(extras)

        # Disconnect Serial Debug (Stub required so BIOS is kept happy)
        kwargs['uart_name'] = "stream"

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         clk_freq=sys_clk_freq,
                         csr_data_width=32,
                         **kwargs)

        # connect UART stream to NULL
        self.comb += self.uart.source.ready.eq(1)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = crg = CRG(platform,
                                        sys_clk_freq,
                                        with_usb_pll=True)

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            available_sdram_modules = {
                "MT41K64M16": MT41K64M16,
                "MT41K128M16": MT41K128M16,
                "MT41K256M16": MT41K256M16,
                "MT41K512M16": MT41K512M16,
            }
            sdram_module = available_sdram_modules.get(
                kwargs.get("sdram_device", "MT41K64M16"))

            ddram_pads = platform.request("ddram")
            self.submodules.ddrphy = ECP5DDRPHY(pads=ddram_pads,
                                                sys_clk_freq=sys_clk_freq)
            self.ddrphy.settings.rtt_nom = "disabled"
            self.add_csr("ddrphy")
            if hasattr(ddram_pads, "vccio"):
                self.comb += ddram_pads.vccio.eq(0b111111)
            if hasattr(ddram_pads, "gnd"):
                self.comb += ddram_pads.gnd.eq(0)
            self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
            self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
            self.add_sdram("sdram",
                           phy=self.ddrphy,
                           module=sdram_module(sys_clk_freq, "1:2"),
                           origin=self.mem_map["main_ram"],
                           size=kwargs.get("max_sdram_size", 0x40000000),
                           l2_cache_size=kwargs.get("l2_size", 8192),
                           l2_cache_min_data_width=kwargs.get(
                               "min_l2_data_width", 128),
                           l2_cache_reverse=True)

        # RGB LED
        self.submodules.rgb = RGB(platform.request("rgb_led", 0))
        #self.submodules.gpio = GPIOTristateCustom(platform.request("gpio", 0))

        self.submodules.gpio = IOPort(platform.request("gpio", 0))

        try:
            self.submodules.button = GPIOIn(platform.request("usr_btn"))
        except:
            ...

        # Analog Mux
        #self.submodules.asense = AnalogSense(platform.request("analog"))

        # drive PROGRAMN HIGH
        self.comb += platform.request("rst_n").eq(1)

        # The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
        # for doing writes.
        spi_pads = platform.request("spiflash4x")
        self.submodules.lxspi = spi_flash.SpiFlashDualQuad(spi_pads,
                                                           dummy=6,
                                                           endianness="little")
        self.lxspi.add_clk_primitive(platform.device)
        self.register_mem("spiflash",
                          self.mem_map["spiflash"],
                          self.lxspi.bus,
                          size=16 * 1024 * 1024)

        # Attach USB to a seperate CSR bus that's decoupled from our CPU clock
        usb_pads = platform.request("usb")
        usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
        self.submodules.usb0 = CSRClockDomainWrapper(usb_iobuf)
        self.comb += self.cpu.interrupt[self.interrupt_map['usb']].eq(
            self.usb0.irq)

        from litex.soc.integration.soc_core import SoCRegion
        self.bus.add_slave(
            'usb', self.usb0.bus,
            SoCRegion(origin=0x90000000, size=0x1000, cached=False))

        self.constants[
            "FLASH_BOOT_ADDRESS"] = self.mem_map['spiflash'] + 0x00100000
예제 #11
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    def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs):
        # Board Revision ---------------------------------------------------------------------------
        revision = kwargs.get("revision", "0.2")
        device = kwargs.get("device", "25F")

        platform = orangecrab.Platform(revision=revision,
                                       device=device,
                                       toolchain=toolchain)

        # Serial -----------------------------------------------------------------------------------
        #platform.add_extension(orangecrab.feather_serial)

        # USB hardware Abstract Control Model.
        kwargs['uart_name'] = "usb_acm"

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         clk_freq=sys_clk_freq,
                         csr_data_width=32,
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = crg = CRG(platform,
                                        sys_clk_freq,
                                        with_usb_pll=True)

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if 1:
            if not self.integrated_main_ram_size:
                available_sdram_modules = {
                    'MT41K64M16': MT41K64M16,
                    'MT41K128M16': MT41K128M16,
                    'MT41K256M16': MT41K256M16
                }
                sdram_module = available_sdram_modules.get(
                    kwargs.get("sdram_device", "MT41K64M16"))

                ddr_pads = platform.request("ddram")
                self.submodules.ddrphy = ECP5DDRPHY(ddr_pads,
                                                    sys_clk_freq=sys_clk_freq)
                self.add_csr("ddrphy")
                self.add_constant("ECP5DDRPHY")
                self.comb += crg.stop.eq(self.ddrphy.init.stop)
                self.comb += crg.reset.eq(self.ddrphy.init.reset)
                self.add_sdram("sdram",
                               phy=self.ddrphy,
                               module=sdram_module(sys_clk_freq, "1:2"),
                               origin=self.mem_map["main_ram"],
                               size=kwargs.get("max_sdram_size", 0x40000000),
                               l2_cache_size=kwargs.get("l2_size", 8192),
                               l2_cache_min_data_width=kwargs.get(
                                   "min_l2_data_width", 128),
                               l2_cache_reverse=True)

                # Virtual power pins - suggested to reduce SSO noise
                self.comb += ddr_pads.vccio.eq(0b111111)
                self.comb += ddr_pads.gnd.eq(0)

        # Add extra pin definitions
        platform.add_extension(extras)

        # RGB LED
        led = platform.request("rgb_led", 0)
        self.submodules.gpio_led = GPIOTristate(Cat(led.r, led.g, led.b))

        # i2c
        self.submodules.i2c = I2CMaster(platform.request("i2c"))

        # SDR processor
        self.submodules.sdr = sdr(platform.request("ad9203"),
                                  platform.request("pdm_out"))
        platform.add_source_dir('vsrc')

        # Controllable Self Reset
        reset_code = Signal(32, reset=0)
        self.submodules.self_reset = GPIOOut(reset_code)
        self.comb += platform.request("rst_n").eq(reset_code != 0xAA550001)

        self.submodules.button = GPIOIn(platform.request("usr_btn"))

        # The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
        # for doing writes.
        spi_pads = platform.request("spiflash4x")
        self.submodules.lxspi = spi_flash.SpiFlashDualQuad(spi_pads,
                                                           dummy=6,
                                                           endianness="little")
        self.lxspi.add_clk_primitive(platform.device)
        self.register_mem("spiflash",
                          self.mem_map["spiflash"],
                          self.lxspi.bus,
                          size=16 * 1024 * 1024)

        # Add GIT repo to the firmware
        git_rev_cmd = subprocess.Popen(["git", "rev-parse", "--short", "HEAD"],
                                       stdout=subprocess.PIPE,
                                       stderr=subprocess.PIPE)
        (git_stdout, _) = git_rev_cmd.communicate()
        self.add_constant('REPO_GIT_SHA1',
                          git_stdout.decode('ascii').strip('\n'))
예제 #12
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    def __init__(self, platform, clk_freq):

        # Work out how many LEDs this board has
        user_leds = []
        while True:
            try:
                user_leds.append(platform.request("user_led", len(user_leds)))
            except ConstraintError:
                break

        if user_leds:
            leds = Signal(len(user_leds))
            self.submodules.leds = GPIOOut(leds)
            for i in range(0, len(user_leds)):
                self.comb += [
                    user_leds[i].eq(leds[i]),
                ]

        # Work out how many switches this board has
        user_sws = []
        while True:
            try:
                user_sws.append(platform.request("user_sw", len(user_sws)))
            except ConstraintError:
                break

        if user_sws:
            switches = Signal(len(user_sws))
            self.submodules.switches = GPIOIn(switches)
            for i in range(0, len(user_sws)):
                self.comb += [
                    switches[i].eq(~user_sws[i]),
                ]

        # Work out how many push buttons this board has
        user_btns = []
        while True:
            try:
                user_btns.append(platform.request("user_btn", len(user_btns)))
            except ConstraintError:
                break

        if user_btns:
            self.submodules.buttons_ev = EventManager()

            _10ms = int(clk_freq * (10e-3))

            for i in range(0, len(user_btns)):
                btn_ev = EventSourceProcess()
                btn_timer = WaitTimer(_10ms)

                setattr(self.buttons_ev, "btn_ev{}".format(i), btn_ev)

                self.comb += [
                    btn_timer.wait.eq(user_btns[i]),
                    btn_ev.trigger.eq(~btn_timer.done),
                ]

                self.submodules += [btn_timer]

            self.buttons_ev.finalize()