def __init__(self,
sys_clk_freq=int(27e6),
with_hyperram=False,
with_led_chaser=True,
with_video_terminal=True,
**kwargs):
platform = tang_nano_4k.Platform()
if "cpu_type" in kwargs and kwargs["cpu_type"] == "gowin_emcu":
kwargs["with_uart"] = False # CPU has own UART
kwargs[
"integrated_sram_size"] = 0 # SRAM is directly attached to CPU
kwargs[
"integrated_rom_size"] = 0 # boot flash directly attached to CPU
else:
# Disable Integrated ROM
kwargs["integrated_rom_size"] = 0
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Tang Nano 4K",
**kwargs)
if self.cpu_type == 'vexriscv':
assert self.cpu_variant == 'minimal', 'use --cpu-variant=minimal to fit into number of BSRAMs'
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_video_pll=with_video_terminal)
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import W25Q32
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="1x",
module=W25Q32(Codes.READ_1_1_1),
with_master=False)
if self.cpu_type == "gowin_emcu":
self.cpu.connect_uart(platform.request("serial"))
else:
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region(
"rom",
SoCRegion(origin=self.bus.regions["spiflash"].origin,
size=32 * kB,
linker=True))
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# HyperRAM ---------------------------------------------------------------------------------
if with_hyperram:
class HyperRAMPads:
def __init__(self):
self.clk = Signal()
self.rst_n = platform.request("O_hpram_reset_n")
self.dq = platform.request("IO_hpram_dq")
self.cs_n = platform.request("O_hpram_cs_n")
self.rwds = platform.request("IO_hpram_rwds")
hyperram_pads = HyperRAMPads()
self.comb += platform.request("O_hpram_ck").eq(hyperram_pads.clk)
self.comb += platform.request("O_hpram_ck_n").eq(
~hyperram_pads.clk)
self.submodules.hyperram = HyperRAM(hyperram_pads)
self.bus.add_slave("main_ram",
slave=self.hyperram.bus,
region=SoCRegion(origin=0x40000000,
size=8 * 1024 * 1024))
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoHDMIPHY(platform.request("hdmi"),
clock_domain="hdmi")
self.add_video_colorbars(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="hdmi")
#self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi") # FIXME: Free up BRAMs.
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
sys_clk_freq=int(75e6),
with_spi_flash=False,
with_ethernet=False,
with_etherbone=False,
eth_phy=0,
eth_ip="192.168.1.50",
with_led_chaser=True,
**kwargs):
platform = efinix_trion_t120_bga576_dev_kit.Platform()
# USBUART PMOD as Serial--------------------------------------------------------------------
platform.add_extension(
efinix_trion_t120_bga576_dev_kit.usb_pmod_io("pmod_e"))
kwargs["uart_name"] = "usb_uart"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Efinix Trion T120 BGA576 Dev Kit",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x",
module=W25Q128JV(Codes.READ_1_1_4),
with_master=True)
platform.toolchain.excluded_ios.append(
platform.lookup_request("spiflash4x").dq)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# Tristate Test ----------------------------------------------------------------------------
from litex.build.generic_platform import Subsignal, Pins, Misc, IOStandard
from litex.soc.cores.bitbang import I2CMaster
platform.add_extension([(
"i2c",
0,
Subsignal("sda", Pins("T12")),
Subsignal("scl", Pins("V11")),
IOStandard("3.3_V_LVTTL_/_LVCMOS"),
)])
self.submodules.i2c = I2CMaster(pads=platform.request("i2c"))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
platform=platform,
clock_pads=platform.request("eth_clocks", eth_phy),
pads=platform.request("eth", eth_phy),
with_hw_init_reset=False)
if with_ethernet:
self.add_ethernet(phy=self.ethphy, software_debug=False)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# FIXME: Avoid this.
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth_clocks").tx)
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth_clocks").rx)
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth").tx_data)
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth").rx_data)
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth").mdio)
# LPDDR3 SDRAM -----------------------------------------------------------------------------
if not self.integrated_main_ram_size:
# DRAM / PLL Blocks.
# ------------------
dram_pll_refclk = platform.request("dram_pll_refclk")
platform.toolchain.excluded_ios.append(dram_pll_refclk)
self.platform.toolchain.additional_sdc_commands.append(
f"create_clock -period {1e9/50e6} dram_pll_refclk")
from litex.build.efinix import InterfaceWriterBlock, InterfaceWriterXMLBlock
import xml.etree.ElementTree as et
class PLLDRAMBlock(InterfaceWriterBlock):
@staticmethod
def generate():
return """
design.create_block("dram_pll", block_type="PLL")
design.set_property("dram_pll", {"REFCLK_FREQ":"50.0"}, block_type="PLL")
design.gen_pll_ref_clock("dram_pll", pll_res="PLL_BR0", refclk_src="EXTERNAL", refclk_name="dram_pll_clkin", ext_refclk_no="0")
design.set_property("dram_pll","LOCKED_PIN","dram_pll_locked", block_type="PLL")
design.set_property("dram_pll","RSTN_PIN","dram_pll_rst_n", block_type="PLL")
design.set_property("dram_pll", {"CLKOUT0_PIN" : "dram_pll_CLKOUT0"}, block_type="PLL")
design.set_property("dram_pll","CLKOUT0_PHASE","0","PLL")
calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"})
"""
platform.toolchain.ifacewriter.blocks.append(PLLDRAMBlock())
class DRAMXMLBlock(InterfaceWriterXMLBlock):
@staticmethod
def generate(root, namespaces):
# CHECKME: Switch to DDRDesignService?
ddr_info = root.find("efxpt:ddr_info", namespaces)
ddr = et.SubElement(ddr_info,
"efxpt:ddr",
name="ddr_inst1",
ddr_def="DDR_0",
cs_preset_id="173",
cs_mem_type="LPDDR3",
cs_ctrl_width="x32",
cs_dram_width="x32",
cs_dram_density="8G",
cs_speedbin="800",
target0_enable="true",
target1_enable="true",
ctrl_type="none")
gen_pin_target0 = et.SubElement(ddr,
"efxpt:gen_pin_target0")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wdata",
type_name=f"WDATA_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wready",
type_name=f"WREADY_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wid",
type_name=f"WID_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_bready",
type_name=f"BREADY_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rdata",
type_name=f"RDATA_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_aid",
type_name=f"AID_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_bvalid",
type_name=f"BVALID_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rlast",
type_name=f"RLAST_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_bid",
type_name=f"BID_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_asize",
type_name=f"ASIZE_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_atype",
type_name=f"ATYPE_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_aburst",
type_name=f"ABURST_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wvalid",
type_name=f"WVALID_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wlast",
type_name=f"WLAST_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_aaddr",
type_name=f"AADDR_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rid",
type_name=f"RID_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_avalid",
type_name=f"AVALID_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rvalid",
type_name=f"RVALID_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_alock",
type_name=f"ALOCK_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rready",
type_name=f"RREADY_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rresp",
type_name=f"RRESP_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wstrb",
type_name=f"WSTRB_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_aready",
type_name=f"AREADY_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_alen",
type_name=f"ALEN_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi_clk",
type_name=f"ACLK_0",
is_bus="false",
is_clk="true",
is_clk_invert="false")
gen_pin_target1 = et.SubElement(ddr,
"efxpt:gen_pin_target1")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wdata",
type_name=f"WDATA_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wready",
type_name=f"WREADY_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wid",
type_name=f"WID_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_bready",
type_name=f"BREADY_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rdata",
type_name=f"RDATA_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_aid",
type_name=f"AID_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_bvalid",
type_name=f"BVALID_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rlast",
type_name=f"RLAST_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_bid",
type_name=f"BID_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_asize",
type_name=f"ASIZE_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_atype",
type_name=f"ATYPE_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_aburst",
type_name=f"ABURST_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wvalid",
type_name=f"WVALID_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wlast",
type_name=f"WLAST_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_aaddr",
type_name=f"AADDR_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rid",
type_name=f"RID_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_avalid",
type_name=f"AVALID_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rvalid",
type_name=f"RVALID_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_alock",
type_name=f"ALOCK_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rready",
type_name=f"RREADY_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rresp",
type_name=f"RRESP_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wstrb",
type_name=f"WSTRB_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_aready",
type_name=f"AREADY_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_alen",
type_name=f"ALEN_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi_clk",
type_name=f"ACLK_1",
is_bus="false",
is_clk="true",
is_clk_invert="false")
gen_pin_config = et.SubElement(ddr, "efxpt:gen_pin_config")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SEQ_RST",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SCL_IN",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SEQ_START",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="RSTN",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SDA_IN",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SDA_OEN",
is_bus="false")
cs_fpga = et.SubElement(ddr, "efxpt:cs_fpga")
et.SubElement(cs_fpga,
"efxpt:param",
name="FPGA_ITERM",
value="120",
value_type="str")
et.SubElement(cs_fpga,
"efxpt:param",
name="FPGA_OTERM",
value="34",
value_type="str")
cs_memory = et.SubElement(ddr, "efxpt:cs_memory")
et.SubElement(cs_memory,
"efxpt:param",
name="RTT_NOM",
value="RZQ/2",
value_type="str")
et.SubElement(cs_memory,
"efxpt:param",
name="MEM_OTERM",
value="40",
value_type="str")
et.SubElement(cs_memory,
"efxpt:param",
name="CL",
value="RL=6/WL=3",
value_type="str")
timing = et.SubElement(ddr, "efxpt:cs_memory_timing")
et.SubElement(timing,
"efxpt:param",
name="tRAS",
value="42.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRC",
value="60.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRP",
value="18.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRCD",
value="18.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tREFI",
value="3.900",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRFC",
value="210.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRTP",
value="10.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tWTR",
value="10.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRRD",
value="10.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tFAW",
value="50.000",
value_type="float")
cs_control = et.SubElement(ddr, "efxpt:cs_control")
et.SubElement(cs_control,
"efxpt:param",
name="AMAP",
value="ROW-COL_HIGH-BANK-COL_LOW",
value_type="str")
et.SubElement(cs_control,
"efxpt:param",
name="EN_AUTO_PWR_DN",
value="Off",
value_type="str")
et.SubElement(cs_control,
"efxpt:param",
name="EN_AUTO_SELF_REF",
value="No",
value_type="str")
cs_gate_delay = et.SubElement(ddr, "efxpt:cs_gate_delay")
et.SubElement(cs_gate_delay,
"efxpt:param",
name="EN_DLY_OVR",
value="No",
value_type="str")
et.SubElement(cs_gate_delay,
"efxpt:param",
name="GATE_C_DLY",
value="3",
value_type="int")
et.SubElement(cs_gate_delay,
"efxpt:param",
name="GATE_F_DLY",
value="0",
value_type="int")
platform.toolchain.ifacewriter.xml_blocks.append(DRAMXMLBlock())
# DRAM Rst.
# ---------
dram_pll_rst_n = platform.add_iface_io("dram_pll_rst_n")
self.comb += dram_pll_rst_n.eq(platform.request("user_btn", 1))
# DRAM AXI-Ports.
# --------------
for n, data_width in {
0: 256, # target0: 256-bit.
1: 128, # target1: 128-bit
}.items():
axi_port = axi.AXIInterface(data_width=data_width,
address_width=28,
id_width=8) # 256MB.
ios = [(
f"axi{n}",
0,
Subsignal("wdata", Pins(data_width)),
Subsignal("wready", Pins(1)),
Subsignal("wid", Pins(8)),
Subsignal("bready", Pins(1)),
Subsignal("rdata", Pins(data_width)),
Subsignal("aid", Pins(8)),
Subsignal("bvalid", Pins(1)),
Subsignal("rlast", Pins(1)),
Subsignal("bid", Pins(8)),
Subsignal("asize", Pins(3)),
Subsignal("atype", Pins(1)),
Subsignal("aburst", Pins(2)),
Subsignal("wvalid", Pins(1)),
Subsignal("aaddr", Pins(32)),
Subsignal("rid", Pins(8)),
Subsignal("avalid", Pins(1)),
Subsignal("rvalid", Pins(1)),
Subsignal("alock", Pins(2)),
Subsignal("rready", Pins(1)),
Subsignal("rresp", Pins(2)),
Subsignal("wstrb", Pins(data_width // 8)),
Subsignal("aready", Pins(1)),
Subsignal("alen", Pins(8)),
Subsignal("wlast", Pins(1)),
)]
io = platform.add_iface_ios(ios)
rw_n = axi_port.ar.valid
self.comb += [
# Pseudo AW/AR Channels.
io.atype.eq(~rw_n),
io.aaddr.eq(Mux(rw_n, axi_port.ar.addr, axi_port.aw.addr)),
io.aid.eq(Mux(rw_n, axi_port.ar.id, axi_port.aw.id)),
io.alen.eq(Mux(rw_n, axi_port.ar.len, axi_port.aw.len)),
io.asize.eq(Mux(rw_n, axi_port.ar.size, axi_port.aw.size)),
io.aburst.eq(
Mux(rw_n, axi_port.ar.burst, axi_port.aw.burst)),
io.alock.eq(Mux(rw_n, axi_port.ar.lock, axi_port.aw.lock)),
io.avalid.eq(
Mux(rw_n, axi_port.ar.valid, axi_port.aw.valid)),
axi_port.aw.ready.eq(~rw_n & io.aready),
axi_port.ar.ready.eq(rw_n & io.aready),
# R Channel.
axi_port.r.id.eq(io.rid),
axi_port.r.data.eq(io.rdata),
axi_port.r.last.eq(io.rlast),
axi_port.r.resp.eq(io.rresp),
axi_port.r.valid.eq(io.rvalid),
io.rready.eq(axi_port.r.ready),
# W Channel.
io.wid.eq(axi_port.w.id),
io.wstrb.eq(axi_port.w.strb),
io.wdata.eq(axi_port.w.data),
io.wlast.eq(axi_port.w.last),
io.wvalid.eq(axi_port.w.valid),
axi_port.w.ready.eq(io.wready),
# B Channel.
axi_port.b.id.eq(io.bid),
axi_port.b.valid.eq(io.bvalid),
io.bready.eq(axi_port.b.ready),
]
# Connect AXI interface to the main bus of the SoC.
axi_lite_port = axi.AXILiteInterface(data_width=data_width,
address_width=28)
self.submodules += axi.AXILite2AXI(axi_lite_port, axi_port)
self.bus.add_slave(f"target{n}", axi_lite_port,
SoCRegion(origin=0x4000_0000 +
0x1000_0000 * n,
size=0x1000_0000)) # 256MB.
# Use DRAM's target0 port as Main Ram -----------------------------------------------------
self.bus.add_region(
"main_ram",
SoCRegion(
origin=0x4000_0000,
size=0x1000_0000, # 256MB.
linker=True))
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
platform = alveo_u250.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Alveo U250",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USPDDRPHY(
platform.request("ddram"),
memtype="DDR4",
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=500e6,
is_rdimm=True)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------
self.add_ram("firmware_ram", 0x20000000, 0x8000)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
# PHY
self.submodules.pcie_phy = USPPCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# Endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(
self.pcie_phy, max_pending_requests=8)
# Wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(
self.pcie_endpoint, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma0")
self.add_constant("DMA_CHANNELS", 1)
# MSI
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, platform, with_pcie=False, **kwargs):
sys_clk_freq = int(100e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Acorn CLE 215+",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K512M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
# PHY
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
self.pcie_phy.add_timing_constraints(platform)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
self.comb += platform.request("pcie_clkreq_n").eq(0)
# Endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(
self.pcie_phy, max_pending_requests=8)
# Wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(
self.pcie_endpoint, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma0")
# DMA1
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma1")
self.add_constant("DMA_CHANNELS", 2)
# MSI
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
with_ethernet=True,
with_etherbone=False,
eth_phy=0,
**kwargs):
sys_clk_freq = int(75e6)
platform = atlys.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Atlys",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
memtype="DDR2",
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT47H64M16(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192),
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
from liteeth.phy import LiteEthPHYGMIIMII
self.submodules.ethphy = LiteEthPHYGMIIMII(
clock_pads=self.platform.request("eth_clocks", eth_phy),
pads=self.platform.request("eth", eth_phy),
clk_freq=int(self.sys_clk_freq))
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_platform_command(
"""
NET "{eth_clocks_rx}" CLOCK_DEDICATED_ROUTE = FALSE;
NET "{eth_clocks_tx}" CLOCK_DEDICATED_ROUTE = FALSE;
""",
eth_clocks_rx=platform.lookup_request("eth_clocks").rx,
eth_clocks_tx=platform.lookup_request("eth_clocks").tx,
)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
bios_flash_offset,
sys_clk_freq=int(25e6),
sdram_rate="1:1",
**kwargs):
platform = tec0117.Platform()
# Use custom default configuration to fit in LittleBee.
kwargs["integrated_sram_size"] = 0x1000
kwargs["integrated_rom_size"] = 0x6000
kwargs["cpu_type"] = "vexriscv"
kwargs["cpu_variant"] = "lite"
# Set CPU variant / reset address
kwargs[
"cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on TEC0117",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
self.add_spi_flash(mode="1x", dummy_cycles=8)
# Add ROM linker region --------------------------------------------------------------------
# FIXME: SPI Flash does not seem responding, power down set after loading bitstream?
#self.bus.add_region("rom", SoCRegion(
# origin = self.mem_map["spiflash"] + bios_flash_offset,
# size = 32*kB,
# linker = True)
#)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
class SDRAMPads:
def __init__(self):
self.clk = platform.request("O_sdram_clk")
self.cke = platform.request("O_sdram_cke")
self.cs_n = platform.request("O_sdram_cs_n")
self.cas_n = platform.request("O_sdram_cas_n")
self.ras_n = platform.request("O_sdram_ras_n")
self.we_n = platform.request("O_sdram_wen_n")
self.dm = platform.request("O_sdram_dqm")
self.a = platform.request("O_sdram_addr")
self.ba = platform.request("O_sdram_ba")
self.dq = platform.request("IO_sdram_dq")
sdram_pads = SDRAMPads()
self.comb += sdram_pads.clk.eq(
~ClockSignal("sys")) # FIXME: use phase shift from PLL.
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq)
self.add_sdram(
"sdram",
phy=self.sdrphy,
module=MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME.
origin=self.mem_map["main_ram"],
l2_cache_size=128,
l2_cache_min_data_width=256,
)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
*,
sys_clk_freq=int(100e6),
iodelay_clk_freq=200e6,
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
with_hyperram=False,
with_sdcard=False,
with_jtagbone=True,
with_uartbone=False,
with_led_chaser=True,
eth_reset_time,
**kwargs):
platform = datacenter_ddr4_test_board.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on data center test board",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
iodelay_clk_freq=iodelay_clk_freq)
# DDR4 SDRAM RDIMM -------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = A7DDRPHY(
platform.request("ddr4"),
memtype="DDR4",
iodelay_clk_freq=iodelay_clk_freq,
sys_clk_freq=sys_clk_freq,
is_rdimm=True,
)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=256,
size=0x40000000,
)
# HyperRAM ---------------------------------------------------------------------------------
if with_hyperram:
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.bus.add_slave("hyperram",
slave=self.hyperram.bus,
region=SoCRegion(origin=0x20000000,
size=8 * 1024 * 1024))
# SD Card ----------------------------------------------------------------------------------
if with_sdcard:
self.add_sdcard()
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
# Traces between PHY and FPGA introduce ignorable delays of ~0.165ns +/- 0.015ns.
# PHY chip does not introduce delays on TX (FPGA->PHY), however it includes 1.2ns
# delay for RX CLK so we only need 0.8ns to match the desired 2ns.
self.submodules.ethphy = LiteEthS7PHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
rx_delay=0.8e-9,
hw_reset_cycles=math.ceil(
float(eth_reset_time) * self.sys_clk_freq))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# UartBone ---------------------------------------------------------------------------------
if with_uartbone:
self.add_uartbone("serial", baudrate=1e6)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# System I2C (behing multiplexer) ----------------------------------------------------------
i2c_pads = platform.request('i2c')
self.submodules.i2c = I2CMaster(i2c_pads)
def __init__(self,
bios_flash_offset,
sys_clk_freq=int(24e6),
with_led_chaser=True,
with_video_terminal=False,
**kwargs):
platform = icebreaker.Platform()
platform.add_extension(icebreaker.break_off_pmod)
# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on iCEBreaker",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
self.submodules.spram = Up5kSPRAM(size=128 * kB)
self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * kB))
self.bus.add_region(
"sram",
SoCRegion(origin=self.bus.regions["psram"].origin + 0 * kB,
size=64 * kB,
linker=True))
if not self.integrated_main_ram_size:
self.bus.add_region(
"main_ram",
SoCRegion(origin=self.bus.regions["psram"].origin + 64 * kB,
size=64 * kB,
linker=True))
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x",
module=W25Q128JV(Codes.READ_1_1_4),
with_master=False)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region(
"rom",
SoCRegion(origin=self.bus.regions["spiflash"].origin +
bios_flash_offset,
size=32 * kB,
linker=True))
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
platform.add_extension(icebreaker.dvi_pmod)
self.submodules.videophy = VideoDVIPHY(platform.request("dvi"),
clock_domain="sys")
self.add_video_terminal(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="sys")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(200e6), disable_sdram=False, **kwargs):
platform = ted_tfoil.Platform()
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on tfoil",
ident_version=True,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
if not disable_sdram:
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USPDDRPHY(
platform.request("ddram"),
memtype="DDR4",
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=400e6)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT40A1G8(sys_clk_freq, "1:4"),
size=0x40000000,
l2_cache_size=kwargs.get("l2_size", 8192))
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
i2c_master_pads = [
platform.request("i2c_tca9555", 0),
platform.request("i2c_tca9555", 1),
platform.request("i2c_tca9555", 2),
platform.request("i2c_tca9555", 3),
platform.request("i2c_tca9555", 4),
platform.request("i2c_tca9555", 5),
platform.request("i2c_tca9555", 6),
platform.request("i2c_tca9548", 0),
platform.request("i2c_tca9548", 1),
platform.request("i2c_tca9548", 2),
platform.request("i2c_tca9548", 3),
platform.request("i2c_si5341", 0),
platform.request("i2c_si5341", 1),
]
self.submodules.i2c = I2CMasterMP(platform, i2c_master_pads)
self.submodules.sb_tca9548 = GPIOOut(
pads=platform.request_all("tca9548_reset_n"))
sb_si5341_o_pads = Cat([
platform.request("si5341_in_sel_0", 0),
platform.request("si5341_in_sel_0", 1),
platform.request("si5341_syncb", 0),
platform.request("si5341_syncb", 1),
platform.request("si5341_rstb", 0),
platform.request("si5341_rstb", 1),
])
sb_si5341_i_pads = Cat([
platform.request("si5341_lolb", 0),
platform.request("si5341_lolb", 1),
])
self.submodules.sb_si5341_o = GPIOOut(pads=sb_si5341_o_pads)
self.submodules.sb_si5341_i = GPIOIn(pads=sb_si5341_i_pads)
self._add_aurora(platform)
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_daughterboard=False,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
with_jtagbone=True, with_spi_flash=False, **kwargs):
platform = qmtech_xc7a35t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard)
# SoCCore ----------------------------------------------------------------------------------
if (kwargs["uart_name"] == "serial") and (not with_daughterboard):
kwargs["uart_name"] = "gpio_serial"
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on QMTech XC7A35T" + (" + Daughterboard" if with_daughterboard else ""),
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet or with_etherbone, with_video_terminal or with_video_framebuffer)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# The daughterboard has the tx clock wired to a non-clock pin, so we can't help it
self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]")
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import MT25QL128
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=MT25QL128(Codes.READ_1_1_1), with_master=True)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
if not with_daughterboard and kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "jtag_serial"
def __init__(self,
revision="0.2",
device="25F",
sdram_device="MT41K64M16",
sys_clk_freq=int(48e6),
toolchain="trellis",
**kwargs):
platform = orangecrab.Platform(revision=revision,
device=device,
toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
if kwargs["uart_name"] in ["serial", "usb_acm"]:
kwargs["uart_name"] = "usb_acm"
# Defaults to USB ACM through ValentyUSB.
os.system(
"git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri"
)
sys.path.append("valentyusb")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on OrangeCrab",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG
self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
available_sdram_modules = {
"MT41K64M16": MT41K64M16,
"MT41K128M16": MT41K128M16,
"MT41K256M16": MT41K256M16,
"MT41K512M16": MT41K512M16,
}
sdram_module = available_sdram_modules.get(sdram_device)
ddram_pads = platform.request("ddram")
self.submodules.ddrphy = ECP5DDRPHY(
pads=ddram_pads,
sys_clk_freq=sys_clk_freq,
cmd_delay=0 if sys_clk_freq > 64e6 else 100)
self.ddrphy.settings.rtt_nom = "disabled"
self.add_csr("ddrphy")
if hasattr(ddram_pads, "vccio"):
self.comb += ddram_pads.vccio.eq(0b111111)
if hasattr(ddram_pads, "gnd"):
self.comb += ddram_pads.gnd.eq(0)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy=self.ddrphy,
module=sdram_module(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
board="i5",
revision="7.0",
sys_clk_freq=60e6,
with_ethernet=False,
with_etherbone=False,
local_ip="",
remote_ip="",
eth_phy=0,
use_internal_osc=False,
sdram_rate="1:1",
with_video_terminal=False,
with_video_framebuffer=False,
**kwargs):
board = board.lower()
assert board in ["i5"]
if board == "i5":
platform = colorlight_i5.Platform(revision=revision)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
int(sys_clk_freq),
ident="LiteX SoC on Colorlight " + board.upper(),
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
with_video_pll = with_video_terminal or with_video_framebuffer
self.submodules.crg = _CRG(platform,
sys_clk_freq,
use_internal_osc=use_internal_osc,
with_usb_pll=with_usb_pll,
with_video_pll=with_video_pll,
sdram_rate=sdram_rate)
# Leds -------------------------------------------------------------------------------------
ledn = platform.request_all("user_led_n")
self.submodules.leds = LedChaser(pads=ledn, sys_clk_freq=sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
self.add_spi_flash(mode="1x", dummy_cycles=8)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 4096)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=M12L64322A(sys_clk_freq, sdram_rate),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks", eth_phy),
pads=self.platform.request("eth", eth_phy),
tx_delay=0)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
if local_ip:
local_ip = local_ip.split(".")
self.add_constant("LOCALIP1", int(local_ip[0]))
self.add_constant("LOCALIP2", int(local_ip[1]))
self.add_constant("LOCALIP3", int(local_ip[2]))
self.add_constant("LOCALIP4", int(local_ip[3]))
if remote_ip:
remote_ip = remote_ip.split(".")
self.add_constant("REMOTEIP1", int(remote_ip[0]))
self.add_constant("REMOTEIP2", int(remote_ip[1]))
self.add_constant("REMOTEIP3", int(remote_ip[2]))
self.add_constant("REMOTEIP4", int(remote_ip[3]))
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoECP5HDMIPHY(
platform.request("gpdi"), clock_domain="hdmi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="hdmi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="hdmi")
def __init__(self,
device="LFE5U-45F",
revision="2.0",
toolchain="trellis",
sys_clk_freq=int(50e6),
sdram_module_cls="MT48LC16M16",
sdram_rate="1:1",
with_led_chaser=True,
with_video_terminal=False,
with_video_framebuffer=False,
spiflash=False,
**kwargs):
platform = ulx3s.Platform(device=device,
revision=revision,
toolchain=toolchain)
if spiflash:
self.mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on ULX3S",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
with_video_pll = with_video_terminal or with_video_framebuffer
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_usb_pll,
with_video_pll,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=getattr(litedram_modules,
sdram_module_cls)(sys_clk_freq,
sdram_rate),
size=0x40000000,
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_reverse=False)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoECP5HDMIPHY(
platform.request("gpdi"), clock_domain="hdmi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="hdmi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="hdmi")
self.comb += platform.request("ext0p").eq(
self.video_framebuffer.underflow
) # FIXME: Remove, used to debug SDRAM underflows.
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
variant="ep4ce15",
sys_clk_freq=int(50e6),
with_daughterboard=False,
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
with_led_chaser=True,
with_video_terminal=False,
with_video_framebuffer=False,
sdram_rate="1:1",
**kwargs):
platform = qmtech_ep4cex5.Platform(
variant=variant, with_daughterboard=with_daughterboard)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on QMTECH EP4CE15" +
(" + Daughterboard" if with_daughterboard else ""),
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_ethernet=with_ethernet
or with_etherbone,
with_vga=with_video_terminal
or with_video_framebuffer,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=W9825G6KH6(sys_clk_freq, sdram_rate),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"),
clock_domain="vga")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="vga")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
bios_flash_offset,
spi_flash_module="AT25SF161",
sys_clk_freq=int(12e6),
with_led_chaser=True,
**kwargs):
kwargs["uart_name"] = "usb_acm" # Enforce UART to USB-ACM
platform = fomu_pvt.Platform()
# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
# Set CPU variant / reset address
kwargs[
"cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# Serial -----------------------------------------------------------------------------------
# FIXME: do proper install of ValentyUSB.
os.system(
"git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri"
)
sys.path.append("valentyusb")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Fomu",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
self.submodules.spram = Up5kSPRAM(size=128 * kB)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128 * kB))
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import AT25SF161, GD25Q16C, MX25R1635F, W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
# lambdas for lazy module instantiation.
spi_flash_modules = {
"AT25SF161": lambda: AT25SF161(Codes.READ_1_1_4),
"GD25Q16C": lambda: GD25Q16C(Codes.READ_1_1_1),
"MX25R1635F": lambda: MX25R1635F(Codes.READ_1_1_4),
"W25Q128JV": lambda: W25Q128JV(Codes.READ_1_1_4),
}
self.add_spi_flash(mode="4x",
module=spi_flash_modules[spi_flash_module](),
with_master=False)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region(
"rom",
SoCRegion(origin=self.mem_map["spiflash"] + bios_flash_offset,
size=32 * kB,
linker=True))
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led_n"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
sys_clk_freq=int(150e6),
ddram_channel=0,
with_pcie=False,
with_led_chaser=False,
with_hbm=False,
**kwargs):
platform = alveo_u280.Platform()
if with_hbm:
assert 225e6 <= sys_clk_freq <= 450e6
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Alveo U280 (ES1)",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, ddram_channel,
with_hbm)
if with_hbm:
# JTAGBone --------------------------------------------------------------------------------
#self.add_jtagbone(chain=2) # Chain 1 already used by HBM2 debug probes.
# Add HBM Core.
self.submodules.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})(
USPHBM2(platform))
# Get HBM .xci.
os.system(
"wget https://github.com/litex-hub/litex-boards/files/6893157/hbm_0.xci.txt"
)
os.makedirs("ip/hbm", exist_ok=True)
os.system("mv hbm_0.xci.txt ip/hbm/hbm_0.xci")
# Connect four of the HBM's AXI interfaces to the main bus of the SoC.
for i in range(4):
axi_hbm = hbm.axi[i]
axi_lite_hbm = AXILiteInterface(data_width=256,
address_width=33)
self.submodules += AXILite2AXI(axi_lite_hbm, axi_hbm)
self.bus.add_slave(f"hbm{i}", axi_lite_hbm,
SoCRegion(origin=0x4000_0000 +
0x1000_0000 * i,
size=0x1000_0000)) # 256MB.
# Link HBM2 channel 0 as main RAM
self.bus.add_region("main_ram",
SoCRegion(origin=0x4000_0000,
size=0x1000_0000,
linker=True)) # 256MB.
else:
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USPDDRPHY(
platform.request("ddram", ddram_channel),
memtype="DDR4",
cmd_latency=1, # seems to work better with cmd_latency=1
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=600e6,
is_rdimm=True)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
size=0x40000000,
l2_cache_size=kwargs.get("l2_size", 8192))
# Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------
self.add_ram("firmware_ram", 0x20000000, 0x8000)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = USPPCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("gpio_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
uart="crossover",
sys_clk_freq=int(125e6),
with_bist=False,
with_analyzer=False):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteDRAM bench on KC705",
ident_version=True,
integrated_rom_size=0x10000,
integrated_rom_mode="rw",
csr_data_width=32,
uart_name=uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
with_bist=with_bist,
)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial",
clk_freq=100e6,
baudrate=115200,
cd="uart")
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=256,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(62.5e6),
sdram_rate="1:1",
with_hdmi_shield=False,
with_sdram_shield=False,
with_led_chaser=True,
with_video_terminal=False,
with_video_framebuffer=False,
with_video_colorbars=False,
**kwargs):
platform = alchitry_mojo.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Alchitry Mojo",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq, sdram_rate)
# HDMI Shield ------------------------------------------------------------------------------
if with_hdmi_shield:
self.platform.add_extension(alchitry_mojo._hdmi_shield)
# SDRAM Shield -----------------------------------------------------------------------------
if with_sdram_shield:
self.platform.add_extension(alchitry_mojo._sdram_shield)
# Add SDRAM if a shield with RAM has been added
if not self.integrated_main_ram_size and (with_hdmi_shield
or with_sdram_shield):
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate ==
"1:2" else "sys_ps")
self.crg.specials += DDROutput(1, 0,
platform.request("sdram_clock"),
sdram_clk)
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=MT48LC32M8(sys_clk_freq, sdram_rate),
l2_cache_size=kwargs.get("l2_size", 1024))
# HDMI Options -----------------------------------------------------------------------------
if with_hdmi_shield and (with_video_colorbars or with_video_framebuffer
or with_video_terminal):
self.submodules.videophy = VideoS6HDMIPHY(
platform.request("hdmi_out"), clock_domain="hdmi")
if with_video_colorbars:
self.add_video_colorbars(phy=self.videophy,
timings="640x480@60Hz",
clock_domain="hdmi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="640x480@60Hz",
clock_domain="hdmi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="640x480@60Hz",
clock_domain="hdmi")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
device="LFE5U-45F",
revision="2.0",
toolchain="trellis",
sys_clk_freq=int(50e6),
sdram_module_cls="MT48LC16M16",
sdram_rate="1:1",
with_led_chaser=True,
with_video_terminal=False,
with_video_framebuffer=False,
with_spi_flash=False,
**kwargs):
platform = ulx3s.Platform(device=device,
revision=revision,
toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on ULX3S",
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
with_video_pll = with_video_terminal or with_video_framebuffer
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_usb_pll,
with_video_pll,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=getattr(litedram_modules,
sdram_module_cls)(sys_clk_freq,
sdram_rate),
size=0x40000000,
l2_cache_size=kwargs.get("l2_size", 8192))
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"),
clock_domain="hdmi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="hdmi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="hdmi")
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import IS25LP128
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=IS25LP128(Codes.READ_1_1_4))
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
*,
sys_clk_freq=int(50e6),
iodelay_clk_freq=200e6,
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
with_hyperram=False,
with_sdcard=False,
with_jtagbone=True,
with_uartbone=False,
ident_version=True,
**kwargs):
platform = lpddr4_test_board.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on LPDDR4 Test Board",
ident_version=ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
iodelay_clk_freq=iodelay_clk_freq)
# LDDR4 SDRAM ------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = lpddr4.K7LPDDR4PHY(
platform.request("lpddr4"),
iodelay_clk_freq=iodelay_clk_freq,
sys_clk_freq=sys_clk_freq,
)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT53E256M16D1(sys_clk_freq, "1:8"),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=256,
)
# HyperRAM ---------------------------------------------------------------------------------
if with_hyperram:
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.register_mem("hyperram", self.mem_map["hyperram"],
self.hyperram.bus, 8 * 1024 * 1024)
# SD Card ----------------------------------------------------------------------------------
if with_sdcard:
self.add_sdcard()
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
# Traces between PHY and FPGA introduce ignorable delays of ~0.165ns +/- 0.015ns.
# PHY chip does not introduce delays on TX (FPGA->PHY), however it includes 1.2ns
# delay for RX CLK so we only need 0.8ns to match the desired 2ns.
self.submodules.ethphy = LiteEthS7PHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
rx_delay=0.8e-9,
)
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# UartBone ---------------------------------------------------------------------------------
if with_uartbone:
self.add_uartbone("serial", baudrate=1e6)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
sys_clk_freq=int(150e6),
ddram_channel=0,
with_led_chaser=True,
with_pcie=False,
**kwargs):
platform = adi_adrv2crr_fmc.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on ADI ADRV2CRR-FMC",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq, ddram_channel)
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USPDDRPHY(
pads=platform.request("ddram", ddram_channel),
memtype="DDR4",
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=400e6)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT40A512M16(sys_clk_freq, "1:4"),
size=0x40000000,
l2_cache_size=kwargs.get("l2_size", 8192))
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
assert self.csr_data_width == 32
self.submodules.pcie_phy = USPPCIEPHY(platform,
platform.request("pcie_x4"),
speed="gen3",
data_width=128,
bar0_size=0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# Fan --------------------------------------------------------------------------------------
# Full speed is _really_ loud and with this demo bitstream which is almost
# empty, we can slow it way down and still keep the FPGA < 10C above ambient
self.submodules.fan = PWM(default_enable=1,
default_period=2500,
default_width=500)
self.comb += platform.request("fan").pwm_n.eq(~self.fan.pwm)
# SYSMON -----------------------------------------------------------------------------------
self.submodules.sysmon = ZynqUSPSystemMonitor()
# JTAG -------------------------------------------------------------------------------------
self.add_jtagbone()
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
with_sata=False,
**kwargs):
platform = nexys_video.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Nexys Video",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K256M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# IOs
_sata_io = [
# AB09-FMCRAID / https://www.dgway.com/AB09-FMCRAID_E.html
("fmc2sata", 0, Subsignal("clk_p", Pins("LPC:GBTCLK0_M2C_P")),
Subsignal("clk_n", Pins("LPC:GBTCLK0_M2C_N")),
Subsignal("tx_p", Pins("LPC:DP0_C2M_P")),
Subsignal("tx_n", Pins("LPC:DP0_C2M_N")),
Subsignal("rx_p", Pins("LPC:DP0_M2C_P")),
Subsignal("rx_n", Pins("LPC:DP0_M2C_N"))),
]
platform.add_extension(_sata_io)
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
pads=platform.request("fmc2sata"),
gen="gen2",
clk_freq=sys_clk_freq,
data_width=16)
self.add_csr("sata_phy")
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(50e6),
revision="revd",
sdram_rate="1:2",
mister_sdram=None,
with_video_terminal=False,
**kwargs):
platform = terasic_sockit.Platform(revision)
# Defaults to UART over JTAG because serial is attached to the HPS and cannot be used.
if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "jtag_atlantic"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on the Terasic SoCKit",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_sdram=mister_sdram != None,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if mister_sdram == "xs_v22":
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=W9825G6KH6(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
if mister_sdram == "xs_v24":
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=AS4C32M16(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Video Terminal ---------------------------------------------------------------------------
if with_video_terminal:
vga_pads = platform.request("vga")
self.comb += [vga_pads.sync_n.eq(0), vga_pads.blank_n.eq(1)]
self.specials += DDROutput(i1=1,
i2=0,
o=vga_pads.clk,
clk=ClockSignal("vga"))
self.submodules.videophy = VideoVGAPHY(vga_pads,
clock_domain="vga")
self.add_video_terminal(phy=self.videophy,
timings="1024x768@60Hz",
clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
bios_flash_offset,
sys_clk_freq=int(25e6),
sdram_rate="1:1",
**kwargs):
platform = tec0117.Platform()
# Put BIOS in SPIFlash to save BlockRAMs.
kwargs["integrated_rom_size"] = 0
kwargs[
"cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on TEC0117",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
self.add_spi_flash(mode="4x", dummy_cycles=6)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region(
"rom",
SoCRegion(origin=self.mem_map["spiflash"] + bios_flash_offset,
size=32 * kB,
linker=True))
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
class SDRAMPads:
def __init__(self):
self.clk = platform.request("O_sdram_clk")
self.cke = platform.request("O_sdram_cke")
self.cs_n = platform.request("O_sdram_cs_n")
self.cas_n = platform.request("O_sdram_cas_n")
self.ras_n = platform.request("O_sdram_ras_n")
self.we_n = platform.request("O_sdram_wen_n")
self.dm = platform.request("O_sdram_dqm")
self.a = platform.request("O_sdram_addr")
self.ba = platform.request("O_sdram_ba")
self.dq = platform.request("IO_sdram_dq")
sdram_pads = SDRAMPads()
sdram_clk = ClockSignal("sys2x" if sdram_rate == "1:2" else
"sys") # FIXME: use phase shift from PLL.
self.specials += DDROutput(0, 1, sdram_pads.clk, sdram_clk)
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq)
self.add_sdram(
"sdram",
phy=self.sdrphy,
module=MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME.
l2_cache_size=128,
l2_cache_min_data_width=256,
)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
with_video_terminal=False,
with_video_framebuffer=False,
video_timing="640x480@60Hz",
**kwargs):
platform = qmtech_wukong.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on QMTECH Wukong Board",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_video_pll = (with_video_terminal or with_video_framebuffer)
self.submodules.crg = _CRG(
platform,
sys_clk_freq,
with_video_pll=with_video_pll,
pix_clk=video_timings[video_timing]["pix_clk"])
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=sys_clk_freq)
if with_ethernet:
self.add_ethernet(phy=self.ethphy, nrxslots=2)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoS7HDMIPHY(
platform.request("hdmi_out"), clock_domain="hdmi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings=video_timing,
clock_domain="hdmi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings=video_timing,
clock_domain="hdmi")
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
ethernet_phy="rgmii",
**kwargs):
platform = ac701.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on AC701",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
pads=PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
# RGMII Ethernet PHY -------------------------------------------------------------------
if ethernet_phy == "rgmii":
# phy
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# 1000BaseX Ethernet PHY ---------------------------------------------------------------
if ethernet_phy == "1000basex":
# phy
self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0)
self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0)
qpll_settings = QPLLSettings(refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
refclk125 = self.platform.request("gtp_refclk")
refclk125_se = Signal()
self.specials += \
Instance("IBUFDS_GTE2",
i_CEB = 0,
i_I = refclk125.p,
i_IB = refclk125.n,
o_O = refclk125_se)
qpll = QPLL(refclk125_se, qpll_settings)
self.submodules += qpll
self.submodules.ethphy = A7_1000BASEX(
qpll_channel=qpll.channels[0],
data_pads=self.platform.request("sfp", 0),
sys_clk_freq=self.clk_freq)
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(125e6),
ddram_channel=0,
with_led_chaser=True,
with_pcie=False,
with_sata=False,
**kwargs):
platform = xcu1525.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on XCU1525",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, ddram_channel)
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USPDDRPHY(
pads=platform.request("ddram", ddram_channel),
memtype="DDR4",
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=500e6)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT40A512M8(sys_clk_freq, "1:4"),
size=0x40000000,
l2_cache_size=kwargs.get("l2_size", 8192))
# Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions.
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]")
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = USPPCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# IOs
_sata_io = [
# SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter
(
"qsfp2sata",
0,
Subsignal("tx_p", Pins("N9")),
Subsignal("tx_n", Pins("N8")),
Subsignal("rx_p", Pins("N4")),
Subsignal("rx_n", Pins("N3")),
),
]
platform.add_extension(_sata_io)
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
refclk=sata_refclk,
pads=platform.request("qsfp2sata"),
gen="gen2",
clk_freq=sys_clk_freq,
data_width=16)
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
revision="rev0",
device="45F",
sdram_device="MT41K512M16",
with_ethernet=False,
sys_clk_freq=int(75e6),
toolchain="trellis",
**kwargs):
platform = logicbone.Platform(revision=revision,
device=device,
toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
if kwargs["uart_name"] == "usb_acm":
# FIXME: do proper install of ValentyUSB.
os.system(
"git clone https://github.com/gregdavill/valentyusb -b hw_cdc_eptri"
)
sys.path.append("valentyusb")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Logicbone",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
available_sdram_modules = {
"MT41K512M16": MT41K512M16,
#"AS4C1GM8": AS4C1GM8, ## Too many rows, seems to break things.
}
sdram_module = available_sdram_modules.get(sdram_device)
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy=self.ddrphy,
module=sdram_module(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(125e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
with_led_chaser=True,
with_pcie=False,
with_sata=False,
**kwargs):
platform = kcu105.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on KCU105",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USDDRPHY(
platform.request("ddram"),
memtype="DDR4",
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
self.add_sdram("sdram",
phy=self.ddrphy,
module=EDY4016A(sys_clk_freq, "1:4"),
size=0x40000000,
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = KU_1000BASEX(
self.crg.cd_eth.clk,
data_pads=self.platform.request("sfp", 0),
sys_clk_freq=self.clk_freq)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
self.platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = USPCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# IOs
_sata_io = [
# SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter
(
"sfp2sata",
0,
Subsignal("tx_p", Pins("U4")),
Subsignal("tx_n", Pins("U3")),
Subsignal("rx_p", Pins("T2")),
Subsignal("rx_n", Pins("T1")),
),
]
platform.add_extension(_sata_io)
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
refclk=sata_refclk,
pads=platform.request("sfp2sata"),
gen="gen2",
clk_freq=sys_clk_freq,
data_width=16)
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, revision="1.0", device="85F", sdram_device="MT41K64M16", sys_clk_freq=int(60e6),
toolchain="trellis", with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50",
eth_dynamic_ip = False,
with_spi_flash = False,
with_led_chaser = True,
with_syzygy_gpio = True,
**kwargs) :
platform = butterstick.Platform(revision=revision, device=device ,toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "crossover"
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on ButterStick",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
available_sdram_modules = {
"MT41K64M16": MT41K64M16,
"MT41K128M16": MT41K128M16,
"MT41K256M16": MT41K256M16,
"MT41K512M16": MT41K512M16,
}
sdram_module = available_sdram_modules.get(sdram_device)
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy = self.ddrphy,
module = sdram_module(sys_clk_freq, "1:2"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=False)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.comb += platform.request("user_led_color").eq(0b010) # Blue.
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# GPIOs ------------------------------------------------------------------------------------
if with_syzygy_gpio:
platform.add_extension(butterstick.raw_syzygy_io("SYZYGY0"))
self.submodules.gpio = GPIOTristate(platform.request("SYZYGY0"))
