def __init__(self, with_ethernet=False): platform = Platform() sys_clk_freq = int(1e6) SoCCore.__init__( self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="linux", with_uart=False, integrated_rom_size=0x8000, integrated_main_ram_size=0x02000000, # 32MB integrated_main_ram_init=get_mem_data( { "buildroot/Image": "0x00000000", "buildroot/rootfs.cpio": "0x00800000", "buildroot/rv32.dtb": "0x01000000" }, "little")) self.add_constant("SIM", None) # supervisor self.submodules.supervisor = Supervisor() self.add_csr("supervisor") # crg self.submodules.crg = CRG(platform.request("sys_clk")) # machine mode emulator ram emulator_rom = get_mem_data("emulator/emulator.bin", "little") self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"]) # serial self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart", allow_user_defined=True) self.add_interrupt("uart", allow_user_defined=True) # ethernet if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.submodules.ethmac = ethmac self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac")
def __init__(self, **kwargs): platform = sim.Platform() SoCSDRAM.__init__(self, platform, clk_freq=int((1/(platform.default_clk_period))*1000000000), integrated_rom_size=0x8000, ident="LiteX simulation example design", with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) if not self.integrated_main_ram_size: sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_refresh=False)) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
def __init__(self, **kwargs): platform = Platform() sys_clk_freq = int(1e6) SoCCore.__init__( self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="linux", with_uart=False, integrated_rom_size=0xC000, integrated_main_ram_size=0x02000000, # 32MB **kwargs) # supervisor self.submodules.supervisor = Supervisor() self.add_csr("supervisor") # crg self.submodules.crg = CRG(platform.request("sys_clk")) # machine mode emulator ram emulator_rom = get_mem_data("emulator/emulator.bin", "little") self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"]) # serial self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart", allow_user_defined=True) self.add_interrupt("uart", allow_user_defined=True) # Integrate Adder8 self.submodules.adder8 = Adder8() self.add_csr("adder8", 10, allow_user_defined=True) # Integrate CAN # self.submodules.can_ctrl = can_ctrl = SJA1000(platform.request("canif", 0)) # self.add_csr("can_ctrl", 11, allow_user_defined=True) # self.add_interrupt("can_ctrl", 6, allow_user_defined=True) # self.register_mem("can_ctrl", 0x30000000, can_ctrl.bus, 512) # can_ctrl.add_source(platform) # platform.add_verilog_include_path("periphs/verilog/can") # Integrate SPI master self.submodules.spi_master = spi_master = SpiMaster( self.platform.request("spi", 0)) self.add_csr("spi_master", 11, allow_user_defined=True) self.add_interrupt("spi_master", 6, allow_user_defined=True) self.register_mem("spi_master", 0x30000000, spi_master.bus, 32) spi_master.add_source(self.platform) platform.add_verilog_include_path("periphs/verilog/spi")
def __init__(self, platform, **kwargs): dict_set_max(kwargs, 'integrated_rom_size', 0x10000) if kwargs.get('cpu_type', None) == 'mor1kx': dict_set_max(kwargs, 'integrated_rom_size', 0x10000) else: dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x8000) dict_set_max(kwargs, 'firmware_ram_size', 0x10000) if 'firmware_filename' not in kwargs: kwargs[ 'firmware_filename'] = "build/sim_{}_{}/software/firmware/firmware.fbi".format( self.__class__.__name__.lower()[:-3], kwargs.get('cpu_type', 'lm32')) clk_freq = int((1 / (platform.default_clk_period)) * 1000000000) SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # firmware self.submodules.firmware_ram = firmware.FirmwareROM( firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.flash_boot_address = self.mem_map["firmware_ram"] define_flash_constants(self) # sdram sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings(memtype="SDR", dfi_databits=1 * 32, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) controller_settings = ControllerSettings(with_refresh=False) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 1024) self.add_constant("MEMTEST_ADDR_SIZE", 1024) self.add_constant("SIMULATION", 1)
def __init__(self, firmware_ram_size=0x10000, firmware_filename="firmware/firmware.bin", **kwargs): platform = sim.Platform() SoCSDRAM.__init__(self, platform, clk_freq=int((1/(platform.default_clk_period))*1000000000), integrated_rom_size=0x8000, integrated_sram_size=0x8000, with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # firmware self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"]) # sdram sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*32, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) controller_settings = ControllerSettings(with_refresh=False) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 1024) self.add_constant("MEMTEST_ADDR_SIZE", 1024) self.add_constant("SIMULATION", 1) self.submodules.video_out = VideoOutCore(self.sdram.crossbar.get_port()) self.submodules.vga = VGAModel(platform.request("vga")) self.comb += self.video_out.source.connect(self.vga.sink)
def __init__(self, platform, cpu, sim: bool, **kwargs): sys_clk_freq = int(1e9 / platform.default_clk_period) kwargs['with_uart'] = not sim SoCCore.__init__(self, platform, cpu_type=cpu.name, clk_freq=sys_clk_freq, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.gpio_led = gpio.GPIOOut(platform.request("user_led")) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map['main_ram']) if sim: # Serial ----------------------------------------------------------------------------------- self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy, tx_fifo_depth=kwargs["uart_fifo_depth"], rx_fifo_depth=kwargs["uart_fifo_depth"]) self.add_csr("uart") self.add_interrupt("uart")
def __init__(self, **kwargs): platform = Platform() sys_clk_freq = int(1e6) SoCCore.__init__( self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="linux", with_uart=False, integrated_rom_size=0x8000, integrated_main_ram_size=0x02000000, # 32MB integrated_main_ram_init=get_mem_data( { "buildroot/Image": "0x00000000", "buildroot/rootfs.cpio": "0x00800000", "buildroot/rv32.dtb": "0x01000000" }, "little"), **kwargs) self.cpu.use_external_variant("VexRiscv.v") # supervisor self.submodules.supervisor = Supervisor() self.add_csr("supervisor") # crg self.submodules.crg = CRG(platform.request("sys_clk")) # machine mode emulator ram emulator_rom = get_mem_data("emulator/emulator.bin", "little") self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"]) # serial self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart", allow_user_defined=True) self.add_interrupt("uart", allow_user_defined=True)
def main(): parser = argparse.ArgumentParser(description=__doc__) builder_args(parser) MySoc.basesoc_args(parser) parser.add_argument("--trace", action="store_true", help="enable VCD tracing") parser.add_argument("--rom-init", default=None, help="rom_init file") parser.set_defaults( integrated_rom_size=0x8000, integrated_main_ram_size=0x8000, # integrated_sram_size=0, # Litex will complain if 0! cpu_type="vexriscv", platform="cmod_a7_sim", clk_freq=int(1e6), with_uart=False # We will add our own mock uart ) args = parser.parse_args() soc_kwargs = vars(args) if args.rom_init: soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init) soc = MySoc(crg=CRG, **soc_kwargs) # Push in a fake uart soc.submodules.uart_phy = uart.RS232PHYModel(soc.platform.request("serial")) soc.submodules.uart = uart.UART(soc.uart_phy) sim_config = SimConfig(default_clk="sys_clk") # sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"}) sim_config.add_module("serial2console", "serial") # sim_config.add_module("serial2tcp", "serial", args={"port": 55555}) # now you can do these 2 things to get a terminal # telnet localhost 55555 # litex_term socket://localhost:55555 # soc.add_constant("TFTP_SERVER_PORT", int(tftp_port)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=False, sim_config=sim_config, trace=args.trace)
def __init__(self, with_sdram=False, with_ethernet=False, with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50", with_analyzer=False, **kwargs): platform = Platform() sys_clk_freq = int(1e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, ident="LiteX Simulation", ident_version=True, with_uart=False, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # Serial ----------------------------------------------------------------------------------- self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart") self.add_interrupt("uart") # SDRAM ------------------------------------------------------------------------------------ if with_sdram: sdram_module = MT48LC16M16(100e6, "1:1") # use 100MHz timings phy_settings = PhySettings(memtype="SDR", databits=32, dfi_databits=16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) # Reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024) self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024) assert not (with_ethernet and with_etherbone ) # FIXME: fix simulator with 2 ethernet interfaces # Ethernet --------------------------------------------------------------------------------- if with_ethernet: # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # Ethernet MAC ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) if with_etherbone: ethmac = ClockDomainsRenamer({ "eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx" })(ethmac) self.submodules.ethmac = ethmac self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") # Ethernet --------------------------------------------------------------------------------- if with_etherbone: # Ethernet PHY self.submodules.etherbonephy = LiteEthPHYModel( self.platform.request("eth", 0)) # FIXME self.add_csr("etherbonephy") # Ethernet MAC etherbonecore = LiteEthUDPIPCore(self.etherbonephy, mac_address=etherbone_mac_address, ip_address=etherbone_ip_address, clk_freq=sys_clk_freq) self.submodules.etherbonecore = etherbonecore # Etherbone self.submodules.etherbone = LiteEthEtherbone( self.etherbonecore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [ # FIXME: find interesting signals to probe self.cpu.ibus, self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512) self.add_csr("analyzer")
def __init__(self, with_sdram=False, with_ethernet=False, with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50", with_analyzer=False, **kwargs): platform = Platform() sys_clk_freq = int(1e9/platform.default_clk_period) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, ident="LiteX Simulation", ident_version=True, with_uart=False, **kwargs) # crg self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # serial self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # sdram if with_sdram: sdram_module = IS42S16160(sys_clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram( self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_refresh=False)) # reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024) assert not (with_ethernet and with_etherbone) # FIXME: fix simulator with 2 ethernet interfaces # ethernet if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) if with_etherbone: ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac) self.submodules.ethmac = ethmac self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) # etherbone if with_etherbone: # eth phy self.submodules.etherbonephy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME # eth core etherbonecore = LiteEthUDPIPCore(self.etherbonephy, etherbone_mac_address, convert_ip(etherbone_ip_address), sys_clk_freq) if with_ethernet: etherbonecore = ClockDomainsRenamer({"eth_tx": "etherbonephy_eth_tx", "eth_rx": "etherbonephy_eth_rx"})(etherbonecore) self.submodules.etherbonecore = etherbonecore # etherbone self.submodules.etherbone = LiteEthEtherbone(self.etherbonecore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # analyzer if with_analyzer: analyzer_signals = [ # FIXME: find interesting signals to probe self.cpu.ibus, self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__(self, init_memories=False, with_sdram=False, sdram_module="MT48LC16M16", sdram_data_width=32, sdram_verbosity=0, with_ethernet=False): platform = Platform() sys_clk_freq = int(1e6) ram_init = [] if init_memories: ram_init = get_mem_data( { "buildroot/Image": "0x00000000", "buildroot/rootfs.cpio": "0x00800000", "buildroot/rv32.dtb": "0x01000000", }, "little") # SoCSDRAM ---------------------------------------------------------------------------------- SoCSDRAM.__init__( self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="linux", with_uart=False, l2_reverse=False, max_sdram_size=0x10000000, # Limit mapped SDRAM to 256MB for now integrated_rom_size=0x8000, integrated_main_ram_size=0x00000000 if with_sdram else 0x02000000, # 32MB integrated_main_ram_init=[] if (with_sdram or not init_memories) else ram_init) self.add_constant("SIM", None) # Supervisor ------------------------------------------------------------------------------- self.submodules.supervisor = Supervisor() self.add_csr("supervisor") # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # Machine mode emulator RAM ---------------------------------------------------------------- emulator_rom = get_mem_data("emulator/emulator.bin", "little") if init_memories else [] self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"]) # SDRAM ------------------------------------------------------------------------------------ if with_sdram: sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings sdram_module_cls = getattr(litedram_modules, sdram_module) sdram_rate = "1:{}".format( sdram_module_nphases[sdram_module_cls.memtype]) sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) phy_settings = get_sdram_phy_settings(memtype=sdram_module.memtype, data_width=sdram_data_width, clk_freq=sdram_clk_freq) self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module, settings=phy_settings, clk_freq=sdram_clk_freq, verbosity=sdram_verbosity, init=ram_init) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) # FIXME: skip memtest to avoid corrupting memory self.add_constant("MEMTEST_BUS_SIZE", 0) self.add_constant("MEMTEST_ADDR_SIZE", 0) self.add_constant("MEMTEST_DATA_SIZE", 0) # Serial ----------------------------------------------------------------------------------- self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart", use_loc_if_exists=True) self.add_interrupt("uart", use_loc_if_exists=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.submodules.ethmac = ethmac self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_csr("ethmac") self.add_interrupt("ethmac")
def __init__(self, with_sdram=False, with_ethernet=False, with_etherbone=False, etherbone_mac_address=0x10e2d5000001, etherbone_ip_address="192.168.1.51", with_analyzer=False, sdram_module="MT48LC16M16", sdram_init=[], sdram_data_width=32, sdram_verbosity=0, **kwargs): platform = Platform() sys_clk_freq = int(1e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, ident="LiteX Simulation", ident_version=True, l2_reverse=False, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # Serial ----------------------------------------------------------------------------------- self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART( self.uart_phy, tx_fifo_depth=kwargs["uart_fifo_depth"], rx_fifo_depth=kwargs["uart_fifo_depth"]) self.add_csr("uart") self.add_interrupt("uart") # SDRAM ------------------------------------------------------------------------------------ if with_sdram: sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings sdram_module_cls = getattr(litedram_modules, sdram_module) sdram_rate = "1:{}".format( sdram_module_nphases[sdram_module_cls.memtype]) sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) phy_settings = get_sdram_phy_settings(memtype=sdram_module.memtype, data_width=sdram_data_width, clk_freq=sdram_clk_freq) self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module, settings=phy_settings, clk_freq=sdram_clk_freq, verbosity=sdram_verbosity, init=sdram_init) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) # Reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024) self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024) #assert not (with_ethernet and with_etherbone) if with_ethernet and with_etherbone: dw = 8 etherbone_ip_address = convert_ip(etherbone_ip_address) # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # Ethernet MAC self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=dw, interface="hybrid", endianness=self.cpu.endianness, hw_mac=etherbone_mac_address) # SoftCPU self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # HW ethernet self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=dw) self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=dw) self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=dw) self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=dw) # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Ethernet --------------------------------------------------------------------------------- elif with_ethernet: # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # Ethernet MAC ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) if with_etherbone: ethmac = ClockDomainsRenamer({ "eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx" })(ethmac) self.submodules.ethmac = ethmac self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # Etherbone -------------------------------------------------------------------------------- elif with_etherbone: # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) # FIXME self.add_csr("ethphy") # Ethernet Core ethcore = LiteEthUDPIPCore(self.ethphy, mac_address=etherbone_mac_address, ip_address=etherbone_ip_address, clk_freq=sys_clk_freq) self.submodules.ethcore = ethcore # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [self.cpu.ibus, self.cpu.dbus] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512) self.add_csr("analyzer")
def __init__(self, simulate, sdram_init=[], with_analyzer=False): self.simulate = simulate if simulate: platform = litex_platform_n64.N64SimPlatform() else: platform = litex_platform_n64.Platform() sys_clk_freq = int(48e6) kwargs = {} kwargs["clk_freq"] = sys_clk_freq kwargs["cpu_type"] = "vexriscv" kwargs["cpu_variant"] = "minimal" kwargs["integrated_rom_size"] = 0 kwargs["integrated_sram_size"] = 2*kB kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset if simulate: kwargs["with_uart"] = False kwargs["with_ethernet"] = False # SoCMini ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, **kwargs) if simulate: self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart") self.add_interrupt("uart") if not self.integrated_main_ram_size: if simulate: sdram_data_width = 16 sdram_module = IS42S16320(sys_clk_freq, "1:1") phy_settings = get_sdram_phy_settings( memtype = sdram_module.memtype, data_width = sdram_data_width, clk_freq = sys_clk_freq) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings, init=sdram_init) self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024) else: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, module = IS42S16320(sys_clk_freq, "1:1"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x4000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) # CRG -------------------------------------------------------------------------------------- if simulate: self.submodules.crg = CRG(platform.request("sys_clk")) else: self.submodules.crg = _CRG(platform, sys_clk_freq) if simulate: integrated_rom_init = get_mem_data("build/software/bios/bios.bin", "little") self.add_rom("rom", self.cpu.reset_address, len(integrated_rom_init)*4, integrated_rom_init) else: self.submodules.spiflash = SpiFlash(platform.request("spiflash"), dummy=8, endianness="little") self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=8*mB) self.add_csr("spiflash") self.add_memory_region("rom", self.mem_map["spiflash"] + bios_flash_offset, 32*kB, type="cached+linker") # Led -------------------------------------------------------------------------------------- self.submodules.led = GPIOOut(platform.request("io0")) self.add_csr("led") # GPIOs ------------------------------------------------------------------------------------ self.submodules.gpio0 = GPIOOut(platform.request("io1")) self.add_csr("gpio0") self.submodules.gpio1 = GPIOOut(platform.request("io2")) self.add_csr("gpio1") platform.add_extension(_gpios) if with_analyzer: analyzer_signals = [ self.cpu.ibus, self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512) self.add_csr("analyzer")