def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5") parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help='gateware toolchain to use, trellis (default)') builder_args(parser) soc_sdram_args(parser) trellis_args(parser) parser.add_argument("--sys-clk-freq", default=75e6, help="system clock frequency (default=75MHz)") parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") args = parser.parse_args() cls = EthernetSoC if args.with_ethernet else BaseSoC soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = {} if args.toolchain == "trellis": builder_kargs == trellis_argdict(args) vns = builder.build(**builder_kargs) csr_csv = export.get_csr_csv(soc.csr_regions, soc.constants) write_to_file("test/csr.csv", csr_csv) soc.analyzer.export_csv( vns, "test/analyzer.csv") # Export the current analyzer configuration
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ECP5 Evaluation Board") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_core_args(parser) parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default=60MHz)") parser.add_argument("--x5-clk-freq", type=int, help="Use X5 oscillator as system clock at the specified frequency") args = parser.parse_args() soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq = int(float(args.sys_clk_freq)), x5_clk_freq = args.x5_clk_freq, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) vns = builder.build(run=args.build) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf")) csr_csv = export.get_csr_csv(soc.csr_regions, soc.constants) write_to_file("test/csr.csv", csr_csv) soc.analyzer.export_csv(vns, "test/analyzer.csv") # Export the current analyzer configuration
def _generate_csr_map(self): if self.csr_json is not None: csr_dir = os.path.dirname(os.path.realpath(self.csr_json)) os.makedirs(csr_dir, exist_ok=True) write_to_file(self.csr_json, export.get_csr_json(self.soc.csr_regions, self.soc.constants, self.soc.mem_regions)) if self.csr_csv is not None: csr_dir = os.path.dirname(os.path.realpath(self.csr_csv)) os.makedirs(csr_dir, exist_ok=True) write_to_file(self.csr_csv, export.get_csr_csv(self.soc.csr_regions, self.soc.constants, self.soc.mem_regions)) if self.csr_svd is not None: svd_dir = os.path.dirname(os.path.realpath(self.csr_svd)) os.makedirs(svd_dir, exist_ok=True) write_to_file(self.csr_svd, export.get_csr_svd(self.soc))
def _generate_csr_map(self): # JSON Export. if self.csr_json is not None: csr_json_contents = export.get_csr_json( csr_regions=self.soc.csr_regions, constants=self.soc.constants, mem_regions=self.soc.mem_regions) write_to_file(os.path.realpath(self.csr_json), csr_json_contents) # CSV Export. if self.csr_csv is not None: csr_csv_contents = export.get_csr_csv( csr_regions=self.soc.csr_regions, constants=self.soc.constants, mem_regions=self.soc.mem_regions) write_to_file(os.path.realpath(self.csr_csv), csr_csv_contents) # SVD Export. if self.csr_svd is not None: csr_svd_contents = export.get_csr_svd(self.soc) write_to_file(os.path.realpath(self.csr_svd), csr_svd_contents)
csr_data_width=32, with_uart=False, with_timer=False) self.submodules.bridge = UARTWishboneBridge(platform.request("serial"), clk_freq) self.add_wb_master(self.bridge.wishbone) self.submodules.analyzer = LiteScopeAnalyzer(platform.request("bus"), 512) self.submodules.io = LiteScopeIO(16) self.comb += [ self.io.input.eq(platform.request("i")), platform.request("o").eq(self.io.output), ] # define platform/core platform = CorePlatform() core = Core(platform) # generate verilog v_output = platform.get_verilog(core, name="litescope") v_output.write("litescope.v") # generate csr.csv write_to_file( "csr.csv", export.get_csr_csv(core.csr_regions, core.constants, core.mem_regions)) # generate analyzer.csv core.analyzer.export_csv(v_output.ns, "analyzer.csv")
===============================""".format(platform_name, args.target, top_class.__name__, soc.clk_freq / 1000000)) # dependencies if actions["all"]: actions["build-csr-csv"] = True actions["build-bitstream"] = True actions["load-bitstream"] = True if actions["build-bitstream"]: actions["build-csr-csv"] = True if actions["clean"]: subprocess.call(["rm", "-rf", "build/*"]) if actions["build-csr-csv"]: csr_csv = export.get_csr_csv(soc.csr_regions) write_to_file(args.csr_csv, csr_csv) if actions["build-bitstream"]: build_kwargs = dict((k, autotype(v)) for k, v in args.build_option) vns = platform.build(soc, build_name=build_name, **build_kwargs) if hasattr(soc, "do_exit") and vns is not None: if hasattr(soc.do_exit, '__call__'): soc.do_exit(vns) if actions["load-bitstream"]: prog = platform.create_programmer() prog.load_bitstream("build/" + build_name + platform.bitstream_ext)
analyzer_groups = {} # Analyzer group analyzer_groups[0] = [ self.serdes.d0.signals, self.serdes.d1.signals, self.serdes.d2.signals, self.serdes.d3.signals, ] # analyzer self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512) def do_exit(self, vns): self.analyzer.export_csv(vns, "test/analyzer.csv") platform = arty.Platform() soc = LiteScopeSoC(platform) vns = platform.build(soc, run="no-compile" not in sys.argv[1:]) # # Create csr and analyzer files # soc.finalize() csr_csv = export.get_csr_csv(soc.csr_regions, soc.constants) write_to_file("test/csr.csv", csr_csv) soc.do_exit(vns)
csr_data_width=32, with_uart=False, ident="csrdemo", ident_version=True, with_timer=False) # Create a Wishbone bus, bridged to the UART bridge = UARTWishboneBridge(platform.request("serial"), SYS_CLK, baudrate=115200) self.submodules.bridge = bridge self.add_wb_master(bridge.wishbone) # Then wire up the addition self.submodules.adder = Adder() self.add_csr("adder") if __name__ == "__main__": plat = build_platform() top = CSRDemo(plat) top.finalize() plat.build(top) csv = get_csr_csv(top.csr.regions, top.constants) print(csv) with open("build/csr.csv", 'w') as out: out.write(csv)