def __init__(self):
self.csr = csr_bus.Interface()
self.submodules.csrmodule = CSRModule()
self.submodules.csrbankarray = csr_bus.CSRBankArray(
self, self.address_map)
self.submodules.csrcon = csr_bus.Interconnect(
self.csr, self.csrbankarray.get_buses())
def do_finalize(self):
registered_mems = {regions[0] for regions in self._memory_regions}
if self.cpu_type is not None:
for mem in "rom", "sram":
if mem not in registered_mems:
raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem))
if len(self._wb_masters):
# Wishbone
self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
self._wb_slaves, register=True)
# CSR
self.submodules.csrbankarray = csr_bus.CSRBankArray(self,
self.get_csr_dev_address,
data_width=self.csr_data_width, address_width=self.csr_address_width)
self.submodules.csrcon = csr_bus.Interconnect(
self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory)
for name, constant in self.csrbankarray.constants:
self._constants.append(((name + "_" + constant.name).upper(), constant.value.value))
for name, value in sorted(self.config.items(), key=itemgetter(0)):
self._constants.append(("CONFIG_" + name.upper(), value))
# Interrupts
if hasattr(self.cpu_or_bridge, "interrupt"):
for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
if hasattr(self, k):
self.comb += self.cpu_or_bridge.interrupt[v].eq(getattr(self, k).ev.irq)
def do_finalize(self):
# Verify CPU has required memories
registered_mems = {regions[0] for regions in self._memory_regions}
if self.cpu_type is not None:
for mem in "rom", "sram":
if mem not in registered_mems:
raise FinalizeError("CPU needs \"{}\" to be registered with SoC.register_mem()".format(mem))
# Add the Wishbone Masters/Slaves interconnect
if len(self._wb_masters):
self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
self._wb_slaves, register=True, timeout_cycles=self.wishbone_timeout_cycles)
if self.with_ctrl and (self.wishbone_timeout_cycles is not None):
self.comb += self.ctrl.bus_error.eq(self.wishbonecon.timeout.error)
# Collect and create CSRs
self.submodules.csrbankarray = csr_bus.CSRBankArray(self,
self.get_csr_dev_address,
data_width=self.csr_data_width,
address_width=self.csr_address_width,
alignment=self.csr_alignment)
# Add CSRs interconnect
if len(self._csr_masters) != 0:
self.submodules.csrcon = csr_bus.InterconnectShared(
self._csr_masters, self.csrbankarray.get_buses())
# Check and add CSRs regions
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.check_csr_range(name, 0x800*mapaddr)
self.add_csr_region(name, (self.soc_mem_map["csr"] + 0x800*mapaddr) | self.shadow_base,
self.csr_data_width, csrs)
# Check and add Memory regions
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.check_csr_range(name, 0x800*mapaddr)
self.add_csr_region(name + "_" + memory.name_override,
(self.soc_mem_map["csr"] + 0x800*mapaddr) | self.shadow_base,
self.csr_data_width, memory)
# Add CSRs / Config items to constants
for name, constant in self.csrbankarray.constants:
self._constants.append(((name + "_" + constant.name).upper(), constant.value.value))
for name, value in sorted(self.config.items(), key=itemgetter(0)):
self._constants.append(("CONFIG_" + name.upper(), value))
if isinstance(value, str):
self._constants.append(("CONFIG_" + name.upper() + "_" + value, 1))
# Connect interrupts
if hasattr(self, "cpu"):
if hasattr(self.cpu, "interrupt"):
for _name, _id in sorted(self.soc_interrupt_map.items()):
if _name in self.cpu.reserved_interrupts.keys():
continue
if hasattr(self, _name):
module = getattr(self, _name)
assert hasattr(module, 'ev'), "Submodule %s does not have EventManager (xx.ev) module" % _name
self.comb += self.cpu.interrupt[_id].eq(module.ev.irq)
def do_finalize(self):
registered_mems = {regions[0] for regions in self._memory_regions}
if self.cpu_type is not None:
for mem in "rom", "sram":
if mem not in registered_mems:
raise FinalizeError(
"CPU needs a {} to be registered with SoC.register_mem()"
.format(mem))
if len(self._wb_masters):
# Wishbone
self.submodules.wishbonecon = wishbone.InterconnectShared(
self._wb_masters, self._wb_slaves, register=True)
if self.with_ctrl:
self.comb += self.ctrl.bus_error.eq(
self.wishbonecon.timeout.error)
# CSR
self.submodules.csrbankarray = csr_bus.CSRBankArray(
self,
self.get_csr_dev_address,
data_width=self.csr_data_width,
address_width=self.csr_address_width)
if self.csr_expose:
self.submodules.csrcon = csr_bus.InterconnectShared(
[self.csr, self.wishbone2csr.csr],
self.csrbankarray.get_buses())
else:
self.submodules.csrcon = csr_bus.Interconnect(
self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_csr_region(name,
(self.mem_map["csr"] + 0x800 * mapaddr)
| self.shadow_base, self.csr_data_width,
csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_csr_region(name + "_" + memory.name_override,
(self.mem_map["csr"] + 0x800 * mapaddr)
| self.shadow_base, self.csr_data_width,
memory)
for name, constant in self.csrbankarray.constants:
self._constants.append(((name + "_" + constant.name).upper(),
constant.value.value))
for name, value in sorted(self.config.items(), key=itemgetter(0)):
self._constants.append(("CONFIG_" + name.upper(), value))
# Interrupts
if hasattr(self.cpu_or_bridge, "interrupt"):
for interrupt, mod_name in sorted(self.interrupt_rmap.items()):
if mod_name == "nmi":
continue
if hasattr(self, mod_name):
mod_impl = getattr(self, mod_name)
assert hasattr(
mod_impl, 'ev'
), "Submodule %s does not have EventManager (xx.ev) module" % mod_name
self.comb += self.cpu_or_bridge.interrupt[
interrupt].eq(mod_impl.ev.irq)
def __init__(self):
self.csr = csr_bus.Interface(data_width=32, address_width=12)
self.axi = Interface(data_width=32, address_width=14)
self.submodules.holder = CSRHolder()
self.submodules.dut = AXILite2CSR(self.axi, self.csr)
self.submodules.csrbankarray = csr_bus.CSRBankArray(
self, self.map_csr, data_width=32, address_width=12)
self.submodules.csrcon = csr_bus.Interconnect(
self.csr, self.csrbankarray.get_buses())
def do_finalize(self):
# Verify CPU has required memories
if not isinstance(self.cpu, cpu.CPUNone):
for name in ["rom", "sram"]:
if name not in self.mem_regions.keys():
raise FinalizeError(
"CPU needs \"{}\" to be defined as memory or linker region"
.format(name))
# Add the Wishbone Masters/Slaves interconnect
if len(self._wb_masters):
self.submodules.wishbonecon = wishbone.InterconnectShared(
self._wb_masters,
self._wb_slaves,
register=True,
timeout_cycles=self.wishbone_timeout_cycles)
if self.with_ctrl and (self.wishbone_timeout_cycles is not None):
self.comb += self.ctrl.bus_error.eq(
self.wishbonecon.timeout.error)
# Collect and create CSRs
self.submodules.csrbankarray = csr_bus.CSRBankArray(
self,
self.get_csr_dev_address,
data_width=self.csr_data_width,
address_width=self.csr_address_width,
alignment=self.csr_alignment)
# Add CSRs interconnect
if len(self._csr_masters) != 0:
self.submodules.csrcon = csr_bus.InterconnectShared(
self._csr_masters, self.csrbankarray.get_buses())
# Check and add CSRs regions
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.check_csr_range(name, 0x800 * mapaddr)
self.add_csr_region(name,
(self.soc_mem_map["csr"] + 0x800 * mapaddr),
self.csr_data_width, csrs)
# Check and add Memory regions
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.check_csr_range(name, 0x800 * mapaddr)
self.add_csr_region(name + "_" + memory.name_override,
(self.soc_mem_map["csr"] + 0x800 * mapaddr),
self.csr_data_width, memory)
# Sort CSR regions by origin
self.csr_regions = {
k: v
for k, v in sorted(self.csr_regions.items(),
key=lambda item: item[1].origin)
}
# Add CSRs / Config items to constants
for name, constant in self.csrbankarray.constants:
self.add_constant(name.upper() + "_" + constant.name.upper(),
constant.value.value)
for name, value in sorted(self.config.items(), key=itemgetter(0)):
self.add_constant("CONFIG_" + name.upper(), value)
if isinstance(value, str):
self.add_constant("CONFIG_" + name.upper() + "_" + value)
# Connect interrupts
if hasattr(self.cpu, "interrupt"):
for _name, _id in sorted(self.soc_interrupt_map.items()):
if _name in self.cpu.interrupts.keys():
continue
if hasattr(self, _name):
module = getattr(self, _name)
assert hasattr(
module, 'ev'
), "Submodule %s does not have EventManager (xx.ev) module" % _name
self.comb += self.cpu.interrupt[_id].eq(module.ev.irq)
self.constants[_name.upper() + "_INTERRUPT"] = _id
def do_finalize(self):
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info(colorer("Finalized SoC:"))
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info(self.bus)
self.logger.info(self.csr)
self.logger.info(self.irq)
self.logger.info(colorer("-"*80, color="bright"))
# SoC Bus Interconnect ---------------------------------------------------------------------
bus_masters = self.bus.masters.values()
bus_slaves = [(self.bus.regions[n].decoder(self.bus), s) for n, s in self.bus.slaves.items()]
if len(bus_masters) and len(bus_slaves):
self.submodules.bus_interconnect = wishbone.InterconnectShared(
masters = bus_masters,
slaves = bus_slaves,
register = True,
timeout_cycles = self.bus.timeout)
if hasattr(self, "ctrl") and self.bus.timeout is not None:
self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error)
# SoC CSR Interconnect ---------------------------------------------------------------------
self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,
address_map = self.csr.address_map,
data_width = self.csr.data_width,
address_width = self.csr.address_width,
alignment = self.csr.alignment,
paging = self.csr.paging,
soc_bus_data_width = self.bus.data_width)
if len(self.csr.masters):
self.submodules.csr_interconnect = csr_bus.InterconnectShared(
masters = list(self.csr.masters.values()),
slaves = self.csr_bankarray.get_buses())
# Add CSRs regions
for name, csrs, mapaddr, rmap in self.csr_bankarray.banks:
self.csr.add_region(name, SoCCSRRegion(
origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
busword = self.csr.data_width,
obj = csrs))
# Add Memory regions
for name, memory, mapaddr, mmap in self.csr_bankarray.srams:
self.csr.add_region(name + "_" + memory.name_override, SoCCSRRegion(
origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
busword = self.csr.data_width,
obj = memory))
# Sort CSR regions by origin
self.csr.regions = {k: v for k, v in sorted(self.csr.regions.items(), key=lambda item: item[1].origin)}
# Add CSRs / Config items to constants
for name, constant in self.csr_bankarray.constants:
self.add_constant(name + "_" + constant.name, constant.value.value)
# SoC CPU Check ----------------------------------------------------------------------------
if not isinstance(self.cpu, cpu.CPUNone):
for name in ["rom", "sram"]:
if name not in self.bus.regions.keys():
self.logger.error("CPU needs {} Region to be {} as Bus or Linker Region.".format(
colorer(name),
colorer("defined", color="red")))
self.logger.error(self.bus)
raise
# SoC IRQ Interconnect ---------------------------------------------------------------------
if hasattr(self, "cpu"):
if hasattr(self.cpu, "interrupt"):
for name, loc in sorted(self.irq.locs.items()):
if name in self.cpu.interrupts.keys():
continue
if hasattr(self, name):
module = getattr(self, name)
if not hasattr(module, "ev"):
self.logger.error("EventManager {} in {} SubModule.".format(
colorer("not found", color="red"),
colorer(name)))
raise
self.comb += self.cpu.interrupt[loc].eq(module.ev.irq)
self.add_constant(name + "_INTERRUPT", loc)
def __init__(self, num_adcs=2):
# AXI is byte addressed, CSR is word addressed...
self.axi_width = 16
self.csr_width = self.axi_width - 2
self._csr_map = {}
self._csr_reverse_map = {}
self.submodules.offsetdac = OffsetDac()
self.offsetdac_mux = self.offsetdac.mux
self.offsetdac_spi = self.offsetdac.spi
# DEBUG
count = Signal(20)
self.sync.data += [count.eq(count + 1)]
self.debug = Signal(64)
# common across all ADC channels
self.adc_axis_clk = Signal()
self.adc_axis_rst = Signal()
def create_signal(name, signal):
setattr(self, name, signal)
getattr(self, name).name_override = name
return signal
# per-ADC signals
for nadc in range(num_adcs):
adc = create_signal("adc%d" % nadc, Signal(20))
adc_tdata = create_signal("adc%d_tdata" % nadc, Signal(64))
adc_tvalid = create_signal("adc%d_tvalid" % nadc, Signal())
adc_tready = create_signal("adc%d_tready" % nadc, Signal())
adc_tlast = create_signal("adc%d_tlast" % nadc, Signal())
lvds_pads_adc = Record(LVDS_ADC)
for i in range(8):
self.comb += [
lvds_pads_adc.d_p[i].eq(adc[i * 2 + 0]),
lvds_pads_adc.d_n[i].eq(adc[i * 2 + 1]),
]
self.comb += [
lvds_pads_adc.lclk_p.eq(adc[16]),
lvds_pads_adc.lclk_n.eq(adc[17]),
lvds_pads_adc.fclk_p.eq(adc[18]),
lvds_pads_adc.fclk_n.eq(adc[19]),
]
adcif = LvdsReceiver(lvds_pads_adc, nadc)
if nadc == 1:
self.comb += [
self.debug[0:32].eq(adcif.d),
self.debug[32:40].eq(adcif.fclk_preslip),
self.debug[40].eq(adcif.d_valid),
self.debug[41].eq(adcif.d_last),
self.debug[42].eq(adcif.d_ready),
self.debug[45:64].eq(count)
]
self.comb += [
adcif.d_clk.eq(self.adc_axis_clk), # data clock
adcif.d_rst.eq(self.adc_axis_rst), # data reset
adc_tdata.eq(adcif.d),
adc_tvalid.eq(adcif.d_valid),
adcif.d_ready.eq(adc_tready),
adc_tlast.eq(adcif.d_last),
]
setattr(self.submodules, "adcif%d" % nadc, adcif)
self.clock_domains.cd_data = ClockDomain()
self.comb += self.cd_data.clk.eq(self.adc_axis_clk)
self.comb += self.cd_data.rst.eq(self.adc_axis_rst)
self.axi_lite = axi.Interface(data_width=32,
address_width=self.axi_width)
self.csr = csr_bus.Interface(data_width=32,
address_width=self.csr_width)
self.submodules.axi2csr = axi.AXILite2CSR(bus_axi=self.axi_lite,
bus_csr=self.csr)
self.submodules.csrbankarray = csr_bus.CSRBankArray(
self,
self._get_csr_map,
data_width=32,
address_width=self.csr_width)
self.submodules.csrcon = csr_bus.Interconnect(
self.csr, self.csrbankarray.get_buses())
self.ios = set()
for i in self.axi_lite, self.offsetdac_mux, self.offsetdac_spi:
self.ios |= set(i.flatten())
self.ios |= set([self.debug, self.adc_axis_clk, self.adc_axis_rst])
for nadc in range(num_adcs):
for i in "adc%d", "adc%d_tdata", "adc%d_tvalid", "adc%d_tready", "adc%d_tlast":
self.ios.add(getattr(self, i % nadc))
def __init__(self):
# AXI is byte addressed, CSR is word addressed...
self.axi_width = 16
self.csr_width = self.axi_width - 2
self._csr_map = {}
self._csr_reverse_map = {}
self.submodules.offsetdac = OffsetDac()
self.offsetdac_mux = self.offsetdac.mux
self.offsetdac_spi = self.offsetdac.spi
self.adc0 = Signal(20) # DP1A, DN1A, ...DN4B, LCLK, FCLK each p/n
# AXIS ADC0 data
self.adc_axis_clk = Signal()
self.adc_axis_rst = Signal()
self.adc0_tdata = Signal(64)
self.adc0_tvalid = Signal()
self.adc0_tready = Signal()
self.debug = Signal(64)
self.lvds_pads_adc0 = Record(LVDS_ADC)
for i in range(8):
self.comb += [
self.lvds_pads_adc0.d_p[i].eq(self.adc0[i * 2 + 0]),
self.lvds_pads_adc0.d_n[i].eq(self.adc0[i * 2 + 1]),
]
self.comb += [
self.lvds_pads_adc0.lclk_p.eq(self.adc0[16]),
self.lvds_pads_adc0.lclk_n.eq(self.adc0[17]),
self.lvds_pads_adc0.fclk_p.eq(self.adc0[18]),
self.lvds_pads_adc0.fclk_n.eq(self.adc0[19]),
]
self.submodules.lvds_adc0 = LvdsReceiver(self.lvds_pads_adc0)
# wire up AXIS
self.comb += [
self.lvds_adc0.d_clk.eq(self.adc_axis_clk), # data clock
self.lvds_adc0.d_rst.eq(self.adc_axis_rst), # data reset
self.adc0_tdata.eq(self.lvds_adc0.d),
self.adc0_tvalid.eq(self.lvds_adc0.d_valid),
self.lvds_adc0.d_ready.eq(self.adc0_tready)
]
# DEBUG
count = Signal(20)
self.clock_domains.cd_data = ClockDomain()
self.comb += self.cd_data.clk.eq(self.adc_axis_clk)
self.comb += self.cd_data.rst.eq(self.adc_axis_rst)
self.sync.data += [count.eq(count + 1)]
self.comb += [
self.debug[0:32].eq(self.lvds_adc0.d),
self.debug[32:40].eq(self.lvds_adc0.fclk_preslip),
self.debug[40].eq(self.lvds_adc0.d_valid),
self.debug[41].eq(self.adc0_tvalid),
self.debug[42].eq(self.adc0_tready), self.debug[45:64].eq(count)
]
self.axi_lite = axi.Interface(data_width=32,
address_width=self.axi_width)
self.csr = csr_bus.Interface(data_width=32,
address_width=self.csr_width)
self.submodules.axi2csr = axi.AXILite2CSR(bus_axi=self.axi_lite,
bus_csr=self.csr)
self.submodules.csrbankarray = csr_bus.CSRBankArray(
self,
self._get_csr_map,
data_width=32,
address_width=self.csr_width)
self.submodules.csrcon = csr_bus.Interconnect(
self.csr, self.csrbankarray.get_buses())
self.ios = set()
for i in self.axi_lite, self.offsetdac_mux, self.offsetdac_spi:
self.ios |= set(i.flatten())
self.ios |= set([
self.debug, self.adc0, self.adc0_tdata, self.adc0_tvalid,
self.adc0_tready, self.adc_axis_clk, self.adc_axis_rst
])
