def do_finalize(self): if not self.integrated_main_ram_size: if not self._sdram_phy: raise FinalizeError("Need to call SoCSDRAM.register_sdram()") # Arbitrate wishbone interfaces to the DRAM if len(self._wb_sdram_ifs) != 0: self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs, self._wb_sdram) SoCCore.do_finalize(self)
def __init__(self): self.submodules.txmem = wishbone.SRAM(1024) self.submodules.rxmem = wishbone.SRAM(1024) self.sysbus = wishbone.Interface() self.submodules.decoder = wishbone.Decoder(self.sysbus, [ (mem_decoder(0x1000, 1024), self.txmem.bus), (mem_decoder(0x2000, 1024), self.rxmem.bus), ], register=True) self.bus = wishbone.Interface() self.submodules.dma = DMATest() self.submodules.arbiter = wishbone.Arbiter( [self.bus, self.dma.master_bus], self.sysbus)
def __init__(self): self.start = Signal() self.done = Signal() self.len = Signal(32) txbus = wishbone.Interface() rxbus = wishbone.Interface() self.submodules.txs = WishboneByteStreamTX(txbus) self.submodules.rxs = WishboneByteStreamRX(rxbus) self.comb += [ self.txs.len.eq(self.len), self.rxs.len.eq(self.len), self.txs.start.eq(self.start), self.rxs.start.eq(self.start), self.done.eq(self.rxs.done), self.rxs.sink.data.eq(self.txs.source.data), self.rxs.sink.valid.eq(self.txs.source.valid), self.txs.source.ready.eq(self.rxs.sink.ready) ] # csr interface self._length = CSRStorage(32) self._txadr = CSRStorage(32) self._rxadr = CSRStorage(32) self._control = CSRStorage(1) self._status = CSRStorage(1) self.comb += [ self.len.eq(self._length.storage), self.txs.adr.eq(self._txadr.storage[2:]), self.rxs.adr.eq(self._rxadr.storage[2:]), self.start.eq(self._control.storage[0]), ] # take care of start / running flags self.sync += [ If(self.start, self._status.storage[0].eq(1), self._control.storage[0].eq(0)), If(self.done, self._status.storage[0].eq(0)), ] # wishbone interface self.master_bus = wishbone.Interface() self.submodules.arbiter = wishbone.Arbiter([txbus, rxbus], self.master_bus)