def _get_variables_contents(self):
# Helper.
variables_contents = []
def define(k, v):
variables_contents.append("{}={}".format(k, _makefile_escape(v)))
# Define packages and libraries.
define("PACKAGES", " ".join(name for name, src_dir in self.software_packages))
define("PACKAGE_DIRS", " ".join(src_dir for name, src_dir in self.software_packages))
define("LIBS", " ".join(self.software_libraries))
# Define CPU variables.
for k, v in export.get_cpu_mak(self.soc.cpu, self.compile_software):
define(k, v)
# Define SoC/Picolibc/Compiler-RT/Software/Include directories.
picolibc_directory = get_data_mod("software", "picolibc").data_location
compiler_rt_directory = get_data_mod("software", "compiler_rt").data_location
define("SOC_DIRECTORY", soc_directory)
define("PICOLIBC_DIRECTORY", picolibc_directory)
define("COMPILER_RT_DIRECTORY", compiler_rt_directory)
variables_contents.append("export BUILDINC_DIRECTORY")
define("BUILDINC_DIRECTORY", self.include_dir)
for name, src_dir in self.software_packages:
define(name.upper() + "_DIRECTORY", src_dir)
# Define BIOS Options.
for bios_option in self.bios_options:
assert bios_option in ["TERM_NO_HIST", "TERM_MINI", "TERM_NO_COMPLETE"]
define(bios_option, "1")
return "\n".join(variables_contents)
def add_sources(platform, variant="standard"):
vdir = get_data_mod("cpu", "cva6").data_location
# platform.add_sources(
# os.path.join(vdir, "generated-src"),
# CPU_VARIANTS[variant] + ".v",
# CPU_VARIANTS[variant] + ".behav_srams.v",
# )
vdir = os.path.join(
get_data_mod("cpu", "cva6").data_location,
"src")
platform.add_source_dir(vdir)
platform.add_verilog_include_path(vdir)
def add_sources(platform, variant="standard"):
filename = get_data_mod("cpu", "blackparrot").data_file(
"flist_litex.verilator")
with open(filename) as openfileobject:
for line in openfileobject:
temp = line
if (temp[0] == '/' and temp[1] == '/'):
continue
elif ("+incdir+" in temp) :
s1 = line.find('$')
s2 = line.find('/')
dir_ = line[s1:s2]
a = os.popen('echo '+ str(dir_))
dir_start = a.read()
vdir = dir_start[:-1] + line[s2:-1]
print("INCDIR" + vdir)
platform.add_verilog_include_path(vdir) #this line might be changed
elif (temp[0]=='$') :
s2 = line.find('/')
dir_ = line[0:s2]
a = os.popen('echo '+ str(dir_))
dir_start = a.read()
vdir = dir_start[:-1]+ line[s2:-1]
print(vdir)
platform.add_source(vdir) #this line might be changed
elif (temp[0] == '/'):
assert("No support for absolute path for now")
def add_sources(platform, variant="standard"):
vdir = get_data_mod("cpu", "blackparrot").data_location
bp_litex_dir = os.path.join(vdir, "bp_litex")
simulation = 1
if (simulation == 1):
filename = os.path.join(bp_litex_dir, "flist.verilator")
else:
filename = os.path.join(bp_litex_dir, "flist.fpga")
with open(filename) as openfileobject:
for line in openfileobject:
temp = line
if (temp[0] == '/' and temp[1] == '/'):
continue
elif ("+incdir+" in temp):
s1 = line.find('$')
s2 = line.find('/')
dir_ = line[s1:s2]
a = os.popen('echo ' + str(dir_))
dir_start = a.read()
vdir = dir_start[:-1] + line[s2:-1]
platform.add_verilog_include_path(
vdir) #this line might be changed
elif (temp[0] == '$'):
s2 = line.find('/')
dir_ = line[0:s2]
a = os.popen('echo ' + str(dir_))
dir_start = a.read()
vdir = dir_start[:-1] + line[s2:-1]
platform.add_source(vdir) #this line might be changed
elif (temp[0] == '/'):
assert ("No support for absolute path for now")
def generate_netlist():
print(f"Generating cluster netlist")
vdir = get_data_mod("cpu", "vexriscv_smp").data_location
gen_args = []
if(VexRiscvSMP.coherent_dma):
gen_args.append("--coherent-dma")
gen_args.append(f"--cpu-count={VexRiscvSMP.cpu_count}")
gen_args.append(f"--ibus-width={VexRiscvSMP.icache_width}")
gen_args.append(f"--dbus-width={VexRiscvSMP.dcache_width}")
gen_args.append(f"--dcache-size={VexRiscvSMP.dcache_size}")
gen_args.append(f"--icache-size={VexRiscvSMP.icache_size}")
gen_args.append(f"--dcache-ways={VexRiscvSMP.dcache_ways}")
gen_args.append(f"--icache-ways={VexRiscvSMP.icache_ways}")
gen_args.append(f"--litedram-width={VexRiscvSMP.litedram_width}")
gen_args.append(f"--aes-instruction={VexRiscvSMP.aes_instruction}")
gen_args.append(f"--out-of-order-decoder={VexRiscvSMP.out_of_order_decoder}")
gen_args.append(f"--wishbone-memory={VexRiscvSMP.wishbone_memory}")
gen_args.append(f"--fpu={VexRiscvSMP.with_fpu}")
gen_args.append(f"--cpu-per-fpu={VexRiscvSMP.cpu_per_fpu}")
gen_args.append(f"--rvc={VexRiscvSMP.with_rvc}")
gen_args.append(f"--netlist-name={VexRiscvSMP.cluster_name}")
gen_args.append(f"--netlist-directory={vdir}")
gen_args.append(f"--dtlb-size={VexRiscvSMP.dtlb_size}")
gen_args.append(f"--itlb-size={VexRiscvSMP.itlb_size}")
cmd = 'cd {path} && sbt "runMain vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen {args}"'.format(path=os.path.join(vdir, "ext", "VexRiscv"), args=" ".join(gen_args))
if os.system(cmd) != 0:
raise OSError('Failed to run sbt')
def generate_netlist(reset_address):
vdir = get_data_mod("cpu", "naxriscv").data_location
ndir = os.path.join(vdir, "ext", "NaxRiscv")
sdir = os.path.join(vdir, "ext", "SpinalHDL")
NaxRiscv.git_setup("NaxRiscv", ndir,
"https://github.com/SpinalHDL/NaxRiscv.git", "main",
"67389bd0")
NaxRiscv.git_setup("SpinalHDL", sdir,
"https://github.com/SpinalHDL/SpinalHDL.git", "dev",
"62531c60")
gen_args = []
gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")
gen_args.append(f"--netlist-directory={vdir}")
gen_args.append(f"--reset-vector={reset_address}")
gen_args.append(f"--xlen={NaxRiscv.xlen}")
for file in NaxRiscv.scala_paths:
gen_args.append(f"--scala-file={file}")
cmd = f"""cd {ndir} && sbt "runMain naxriscv.platform.LitexGen {" ".join(gen_args)}\""""
print("NaxRiscv generation command :")
print(cmd)
if os.system(cmd) != 0:
raise OSError('Failed to run sbt')
def add_sources(platform, variant):
vdir = get_data_mod("cpu", "lm32").data_location
platform.add_sources(os.path.join(vdir, "rtl"),
"lm32_cpu.v",
"lm32_instruction_unit.v",
"lm32_decoder.v",
"lm32_load_store_unit.v",
"lm32_adder.v",
"lm32_addsub.v",
"lm32_logic_op.v",
"lm32_shifter.v",
"lm32_multiplier.v",
"lm32_mc_arithmetic.v",
"lm32_interrupt.v",
"lm32_ram.v",
"lm32_dp_ram.v",
"lm32_icache.v",
"lm32_dcache.v",
"lm32_debug.v",
"lm32_itlb.v",
"lm32_dtlb.v")
platform.add_verilog_include_path(os.path.join(vdir, "rtl"))
if variant == "minimal":
platform.add_verilog_include_path(os.path.join(vdir, "config_minimal"))
elif variant == "lite":
platform.add_verilog_include_path(os.path.join(vdir, "config_lite"))
elif variant == "standard":
platform.add_verilog_include_path(os.path.join(vdir, "config"))
else:
raise TypeError("Unknown variant {}".format(variant))
def add_sources(platform):
ibexdir = get_data_mod("cpu", "ibex").data_location
platform.add_verilog_include_path(os.path.join(ibexdir, "rtl"))
platform.add_verilog_include_path(
os.path.join(ibexdir, "vendor", "lowrisc_ip", "dv", "sv",
"dv_utils"))
platform.add_verilog_include_path(
os.path.join(ibexdir, "vendor", "lowrisc_ip", "ip", "prim", "rtl"))
platform.add_source(
os.path.join(ibexdir, "syn", "rtl", "prim_clock_gating.v"))
platform.add_sources(
os.path.join(ibexdir, "vendor", "lowrisc_ip", "ip", "prim", "rtl"),
"prim_alert_pkg.sv",
"prim_assert.sv",
"prim_ram_1p_pkg.sv",
)
platform.add_sources(
os.path.join(ibexdir, "rtl"), "ibex_pkg.sv", "ibex_alu.sv",
"ibex_compressed_decoder.sv", "ibex_controller.sv",
"ibex_counter.sv", "ibex_cs_registers.sv", "ibex_csr.sv",
"ibex_decoder.sv", "ibex_ex_block.sv", "ibex_id_stage.sv",
"ibex_if_stage.sv", "ibex_load_store_unit.sv",
"ibex_multdiv_slow.sv", "ibex_multdiv_fast.sv",
"ibex_prefetch_buffer.sv", "ibex_fetch_fifo.sv",
"ibex_register_file_fpga.sv", "ibex_wb_stage.sv", "ibex_core.sv",
"ibex_top.sv")
def generate_netlist(reset_address):
vdir = get_data_mod("cpu", "naxriscv").data_location
ndir = os.path.join(vdir, "ext", "NaxRiscv")
sdir = os.path.join(vdir, "ext", "SpinalHDL")
NaxRiscv.git_setup("NaxRiscv", ndir,
"https://github.com/SpinalHDL/NaxRiscv.git", "dev",
"8b4449f9")
NaxRiscv.git_setup("SpinalHDL", sdir,
"https://github.com/SpinalHDL/SpinalHDL.git", "dev",
"4c024e93")
gen_args = []
gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")
gen_args.append(f"--netlist-directory={vdir}")
gen_args.append(f"--reset-vector={reset_address}")
gen_args.append(f"--xlen={NaxRiscv.xlen}")
for args in NaxRiscv.scala_args:
gen_args.append(f"--scala-args={args}")
if (NaxRiscv.jtag_tap):
gen_args.append(f"--with-jtag-tap")
if (NaxRiscv.jtag_instruction):
gen_args.append(f"--with-jtag-instruction")
if (NaxRiscv.jtag_tap or NaxRiscv.jtag_instruction):
gen_args.append(f"--with-debug")
for file in NaxRiscv.scala_paths:
gen_args.append(f"--scala-file={file}")
cmd = f"""cd {ndir} && sbt "runMain naxriscv.platform.LitexGen {" ".join(gen_args)}\""""
print("NaxRiscv generation command :")
print(cmd)
if os.system(cmd) != 0:
raise OSError('Failed to run sbt')
def _generate_includes(self):
os.makedirs(self.include_dir, exist_ok=True)
os.makedirs(self.generated_dir, exist_ok=True)
if self.soc.cpu_type not in [None, "zynq7000"]:
variables_contents = []
def define(k, v):
variables_contents.append("{}={}\n".format(k, _makefile_escape(v)))
for k, v in export.get_cpu_mak(self.soc.cpu, self.compile_software):
define(k, v)
define(
"COMPILER_RT_DIRECTORY",
get_data_mod("software", "compiler_rt").data_location)
define("SOC_DIRECTORY", soc_directory)
variables_contents.append("export BUILDINC_DIRECTORY\n")
define("BUILDINC_DIRECTORY", self.include_dir)
for name, src_dir in self.software_packages:
define(name.upper() + "_DIRECTORY", src_dir)
for bios_option in self.bios_options:
assert bios_option in ["TERM_NO_HIST", "TERM_MINI", "TERM_NO_COMPLETE"]
define(bios_option, "1")
write_to_file(
os.path.join(self.generated_dir, "variables.mak"),
"".join(variables_contents))
write_to_file(
os.path.join(self.generated_dir, "output_format.ld"),
export.get_linker_output_format(self.soc.cpu))
write_to_file(
os.path.join(self.generated_dir, "regions.ld"),
export.get_linker_regions(self.soc.mem_regions))
write_to_file(
os.path.join(self.generated_dir, "mem.h"),
export.get_mem_header(self.soc.mem_regions))
write_to_file(
os.path.join(self.generated_dir, "soc.h"),
export.get_soc_header(self.soc.constants))
write_to_file(
os.path.join(self.generated_dir, "csr.h"),
export.get_csr_header(
regions = self.soc.csr_regions,
constants = self.soc.constants,
csr_base = self.soc.mem_regions['csr'].origin
)
)
write_to_file(
os.path.join(self.generated_dir, "git.h"),
export.get_git_header()
)
if hasattr(self.soc, "sdram"):
from litedram.init import get_sdram_phy_c_header
write_to_file(os.path.join(self.generated_dir, "sdram_phy.h"),
get_sdram_phy_c_header(
self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing))
def add_sources(self, platform):
vdir = get_data_mod("cpu", "vexriscv_smp").data_location
print(f"VexRiscv cluster : {self.cluster_name}")
if not path.exists(os.path.join(vdir, self.cluster_name + ".v")):
self.generate_netlist()
platform.add_source(os.path.join(vdir, "RamXilinx.v"), "verilog")
platform.add_source(os.path.join(vdir, self.cluster_name + ".v"), "verilog")
def build_cpu_variant_if_needed(variant):
if variant in core.CPU_VARIANTS:
print(f"Variant \"{variant}\" already known.")
else:
#
# TODO: parse "variant" to determine configuration in "gen_args",
# and create a canonical "cpu_filename_base" that is uniquely
# determined by the config.
#
dsz = 4096
isz = 4096
gen_args = []
if "cfu" in variant:
gen_args.append(f"--cfu=true")
gen_args.append(f"--dCacheSize={dsz}")
gen_args.append(f"--iCacheSize={isz}")
cpu_filename_base = "VexRiscv_GEN"
gen_args.append(f"--outputFile={cpu_filename_base}")
cpu_filename = cpu_filename_base + ".v"
print(f"Generating variant \"{variant}\" in file \"{cpu_filename}\".")
cfu_root = os.environ.get('CFU_ROOT')
custom_dir = os.path.join(cfu_root, "soc", "vexriscv")
custom_cpu = os.path.join(custom_dir, cpu_filename)
vdir = get_data_mod("cpu", "vexriscv").data_location
fullpath = os.path.join(vdir, cpu_filename)
#
# build it if needed!
#
if not os.path.exists(custom_cpu):
cmd = 'cd {path} && sbt compile "runMain vexriscv.GenCoreDefault {args}"'.format(
path=custom_dir, args=" ".join(gen_args))
if os.system(cmd) != 0:
raise OSError('Failed to run sbt')
#
# do some patching
# TODO: 'arch' will depend on the CPU config.
#
arch = "rv32im"
abi = "ilp32"
gcc_flags = f"-march={arch} -mabi={abi}"
core.CPU_VARIANTS.update({
variant: cpu_filename_base,
})
core.GCC_FLAGS.update({
variant: gcc_flags,
})
#
# Copy file to where it goes
#
copyfile(custom_cpu, fullpath)
def add_sources(platform):
sdir = os.path.join(
get_data_mod("cpu", "microwatt").data_location,
"sources")
platform.add_sources(sdir,
# Common / Types / Helpers
"decode_types.vhdl",
"wishbone_types.vhdl",
"utils.vhdl",
"common.vhdl",
"helpers.vhdl",
# Fetch
"fetch1.vhdl",
"fetch2.vhdl",
# Instruction/Data Cache
"cache_ram.vhdl",
"plru.vhdl",
"dcache.vhdl",
"icache.vhdl",
# Decode
"insn_helpers.vhdl",
"decode1.vhdl",
"gpr_hazard.vhdl",
"cr_hazard.vhdl",
"control.vhdl",
"decode2.vhdl",
# Register/CR File
"register_file.vhdl",
"crhelpers.vhdl",
"cr_file.vhdl",
# Execute
"ppc_fx_insns.vhdl",
"logical.vhdl",
"rotator.vhdl",
"countzero.vhdl",
"execute1.vhdl",
# Load/Store
"loadstore1.vhdl",
# Multiply/Divide
"multiply.vhdl",
"divider.vhdl",
# Writeback
"writeback.vhdl",
# Core
"core_debug.vhdl",
"core.vhdl",
)
platform.add_source(os.path.join(sdir, "..", "microwatt_wrapper.vhdl"))
def add_sources(self, platform):
vdir = get_data_mod("misc", "usb_ohci").data_location
netlist_name = self.get_netlist_name()
print(f"USB OHCI netlist : {netlist_name}")
if not os.path.exists(os.path.join(vdir, netlist_name + ".v")):
self.generate_netlist()
platform.add_source(os.path.join(vdir, netlist_name + ".v"), "verilog")
def _generate_includes(self):
os.makedirs(self.include_dir, exist_ok=True)
os.makedirs(self.generated_dir, exist_ok=True)
if self.soc.cpu_type is not None:
variables_contents = []
def define(k, v):
variables_contents.append("{}={}\n".format(
k, _makefile_escape(v)))
for k, v in export.get_cpu_mak(self.soc.cpu,
self.compile_software):
define(k, v)
# Distinguish between LiteX and MiSoC.
define("LITEX", "1")
# Distinguish between applications running from main RAM and
# flash for user-provided software packages.
exec_profiles = {"COPY_TO_MAIN_RAM": "0", "EXECUTE_IN_PLACE": "0"}
if "main_ram" in self.soc.mem_regions.keys():
exec_profiles["COPY_TO_MAIN_RAM"] = "1"
else:
exec_profiles["EXECUTE_IN_PLACE"] = "1"
for k, v in exec_profiles.items():
define(k, v)
define("COMPILER_RT_DIRECTORY",
get_data_mod("software", "compiler_rt").data_location)
define("SOC_DIRECTORY", soc_directory)
variables_contents.append("export BUILDINC_DIRECTORY\n")
define("BUILDINC_DIRECTORY", self.include_dir)
for name, src_dir in self.software_packages:
define(name.upper() + "_DIRECTORY", src_dir)
write_to_file(os.path.join(self.generated_dir, "variables.mak"),
"".join(variables_contents))
write_to_file(os.path.join(self.generated_dir, "output_format.ld"),
export.get_linker_output_format(self.soc.cpu))
write_to_file(os.path.join(self.generated_dir, "regions.ld"),
export.get_linker_regions(self.soc.mem_regions))
write_to_file(os.path.join(self.generated_dir, "mem.h"),
export.get_mem_header(self.soc.mem_regions))
write_to_file(os.path.join(self.generated_dir, "soc.h"),
export.get_soc_header(self.soc.constants))
write_to_file(
os.path.join(self.generated_dir, "csr.h"),
export.get_csr_header(self.soc.csr_regions, self.soc.constants))
write_to_file(os.path.join(self.generated_dir, "git.h"),
export.get_git_header())
if hasattr(self.soc, "sdram"):
from litedram.init import get_sdram_phy_c_header
write_to_file(
os.path.join(self.generated_dir, "sdram_phy.h"),
get_sdram_phy_c_header(
self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing))
def add_sources(platform):
cva5_path = get_data_mod("cpu", "cva5").data_location
with open(os.path.join(cva5_path, "tools/compile_order"), "r") as f:
for line in f:
if line.strip() != '':
platform.add_source(os.path.join(cva5_path, line.strip()))
platform.add_source(
os.path.join(cva5_path, "examples/litex/l1_to_wishbone.sv"))
platform.add_source(
os.path.join(cva5_path, "examples/litex/litex_wrapper.sv"))
def add_manifest_sources(platform, manifest):
basedir = get_data_mod("cpu", "cva6").data_location
with open(os.path.join(basedir, manifest), 'r') as f:
for l in f:
res = re.search('\$\{CVA6_REPO_DIR\}/(.+)', l)
if res and not re.match('//', l):
if re.match('\+incdir\+', l):
platform.add_verilog_include_path(os.path.join(basedir, res.group(1)))
else:
platform.add_source(os.path.join(basedir, res.group(1)))
def find_scala_files():
vdir = get_data_mod("cpu", "naxriscv").data_location
for file in NaxRiscv.scala_files:
if os.path.exists(file):
NaxRiscv.scala_paths.append(os.path.abspath(file))
else:
path = os.path.join(vdir, "configs", file)
if os.path.exists(path):
NaxRiscv.scala_paths.append(path)
else:
raise Exception(f"Can't find NaxRiscv's {file}")
def _generate_sim_variables(include_paths):
tapcfg_dir = get_data_mod("misc", "tapcfg").data_location
include = ""
for path in include_paths:
include += "-I" + path + " "
content = """\
SRC_DIR = {}
INC_DIR = {}
TAPCFG_DIRECTORY = {}
""".format(core_directory, include, tapcfg_dir)
tools.write_to_file("variables.mak", content)
def elaborate(reset_address, with_icache, with_dcache, with_muldiv, verilog_filename):
cli_params = []
cli_params.append("--reset-addr={}".format(reset_address))
if with_icache:
cli_params.append("--with-icache")
if with_dcache:
cli_params.append("--with-dcache")
if with_muldiv:
cli_params.append("--with-muldiv")
sdir = get_data_mod("cpu", "minerva").data_location
if subprocess.call(["python3", os.path.join(sdir, "cli.py"), *cli_params, "generate"],
stdout=open(verilog_filename, "w")):
raise OSError("Unable to elaborate Minerva CPU, please check your nMigen/Yosys install")
def add_sources(platform, variant="standard"):
vdir = get_data_mod("cpu", "rocket").data_location
platform.add_sources(
os.path.join(vdir, "generated-src"),
CPU_VARIANTS[variant] + ".v",
CPU_VARIANTS[variant] + ".behav_srams.v",
)
platform.add_sources(
os.path.join(vdir, "vsrc"),
"plusarg_reader.v",
"AsyncResetReg.v",
"EICG_wrapper.v",
)
def __init__(self, platform, variant="standard"):
self.platform = platform
self.variant = variant
self.reset = Signal()
self.idbus = idbus = wishbone.Interface(data_width=64, adr_width=37)
self.periph_buses = [idbus]
self.memory_buses = []
self.cpu_params = dict(
# Clk / Rst.
i_clk_i=ClockSignal("sys"),
i_reset_i=ResetSignal("sys") | self.reset,
# Wishbone (I/D).
i_wbm_dat_i=idbus.dat_r,
o_wbm_dat_o=idbus.dat_w,
i_wbm_ack_i=idbus.ack,
i_wbm_err_i=idbus.err,
i_wbm_rty_i=Open(),
o_wbm_adr_o=idbus.adr,
o_wbm_stb_o=idbus.stb,
o_wbm_cyc_o=idbus.cyc,
o_wbm_sel_o=idbus.sel,
o_wbm_we_o=idbus.we,
o_wbm_cti_o=idbus.cti,
o_wbm_bte_o=idbus.bte,
)
# Copy config loader to /tmp
vdir = get_data_mod("cpu", "blackparrot").data_location
blackparrot = os.path.join(vdir, "black-parrot")
bp_litex = os.path.join(vdir, "bp_litex")
copyfile(os.path.join(bp_litex, "cce_ucode.mem"), "/tmp/cce_ucode.mem")
# Set environmental variables
os.environ["BP"] = blackparrot
os.environ["BP_LITEX_DIR"] = bp_litex
os.environ["BP_COMMON_DIR"] = os.path.join(blackparrot, "bp_common")
os.environ["BP_FE_DIR"] = os.path.join(blackparrot, "bp_fe")
os.environ["BP_BE_DIR"] = os.path.join(blackparrot, "bp_be")
os.environ["BP_ME_DIR"] = os.path.join(blackparrot, "bp_me")
os.environ["BP_TOP_DIR"] = os.path.join(blackparrot, "bp_top")
external = os.path.join(blackparrot, "external")
os.environ["BP_EXTERNAL_DIR"] = external
os.environ["BASEJUMP_STL_DIR"] = os.path.join(external, "basejump_stl")
os.environ["HARDFLOAT_DIR"] = os.path.join(external, "HardFloat")
os.environ["LITEX_FPGA_DIR"] = os.path.join(bp_litex, "fpga")
os.environ["LITEX_SIMU_DIR"] = os.path.join(bp_litex, "simulation")
self.add_sources(platform, variant)
def add_sources(platform, use_ghdl_yosys_plugin=False):
sources = [
# Common / Types / Helpers
"decode_types.vhdl",
"wishbone_types.vhdl",
"utils.vhdl",
"common.vhdl",
"helpers.vhdl",
# XICS controller
"xics.vhdl",
]
sdir = get_data_mod("cpu", "microwatt").data_location
cdir = os.path.dirname(__file__)
if use_ghdl_yosys_plugin:
from litex.build import tools
import subprocess
# ICP
ys = []
ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \\")
for source in sources:
ys.append(os.path.join(sdir, source) + " \\")
ys.append(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl") + " \\")
ys.append("-e xics_icp_wrapper")
ys.append("chformal -assert -remove")
ys.append("write_verilog {}".format(os.path.join(cdir, "xics_icp.v")))
tools.write_to_file(os.path.join(cdir, "xics_icp.ys"), "\n".join(ys))
if subprocess.call(["yosys", "-q", "-m", "ghdl", os.path.join(cdir, "xics_icp.ys")]):
raise OSError("Unable to convert Microwatt XICS ICP controller to verilog, please check your GHDL-Yosys-plugin install")
platform.add_source(os.path.join(cdir, "xics_icp.v"))
# ICS
ys = []
ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \\")
for source in sources:
ys.append(os.path.join(sdir, source) + " \\")
ys.append(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl") + " \\")
ys.append("-e xics_ics_wrapper")
ys.append("chformal -assert -remove")
ys.append("write_verilog {}".format(os.path.join(cdir, "xics_ics.v")))
tools.write_to_file(os.path.join(cdir, "xics_ics.ys"), "\n".join(ys))
if subprocess.call(["yosys", "-q", "-m", "ghdl", os.path.join(cdir, "xics_ics.ys")]):
raise OSError("Unable to convert Microwatt XICS ICP controller to verilog, please check your GHDL-Yosys-plugin install")
platform.add_source(os.path.join(cdir, "xics_ics.v"))
else:
platform.add_sources(sdir, *sources)
platform.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl"))
def generate_netlist(self):
print(f"Generating USB OHCI netlist")
vdir = get_data_mod("misc", "usb_ohci").data_location
gen_args = []
gen_args.append(f"--port-count={len(self.pads.dp)}")
gen_args.append(f"--phy-frequency={self.usb_clk_freq}")
gen_args.append(f"--dma-width={self.dma_data_width}")
gen_args.append(f"--netlist-name={self.get_netlist_name()}")
gen_args.append(f"--netlist-directory={vdir}")
cmd = 'cd {path} && sbt "lib/runMain spinal.lib.com.usb.ohci.UsbOhciWishbone {args}"'.format(
path=os.path.join(vdir, "ext", "SpinalHDL"),
args=" ".join(gen_args))
print("!!! " + cmd)
if os.system(cmd) != 0:
raise OSError('Failed to run sbt')
def _generate_sim_variables(include_paths, extra_mods, extra_mods_path):
tapcfg_dir = get_data_mod("misc", "tapcfg").data_location
include = ""
for path in include_paths:
include += "-I" + path + " "
content = """\
SRC_DIR = {}
INC_DIR = {}
TAPCFG_DIRECTORY = {}
""".format(core_directory, include, tapcfg_dir)
if extra_mods:
modlist = " ".join(extra_mods)
content += "EXTRA_MOD_LIST = " + modlist + "\n"
content += "EXTRA_MOD_BASE_DIR = " + extra_mods_path + "\n"
tools.write_to_file(extra_mods_path + "/variables.mak", content)
tools.write_to_file("variables.mak", content)
def add_sources(self, platform):
vdir = get_data_mod("cpu", "vexriscv_smp").data_location
print(f"VexRiscv cluster : {self.cluster_name}")
if not path.exists(os.path.join(vdir, self.cluster_name + ".v")):
self.generate_netlist()
# Add RAM.
# By default, use Generic RAM implementation.
ram_filename = "Ram_1w_1rs_Generic.v"
# On Altera/Intel platforms, use specific implementation.
from litex.build.altera import AlteraPlatform
if isinstance(platform, AlteraPlatform):
ram_filename = "Ram_1w_1rs_Intel.v"
platform.add_source(os.path.join(vdir, ram_filename), "verilog")
# Add Cluster.
platform.add_source(os.path.join(vdir, self.cluster_name + ".v"),
"verilog")
def generate_netlist():
print(f"Generating cluster netlist")
vdir = get_data_mod("cpu", "vexriscv_smp").data_location
gen_args = []
if(VexRiscvSMP.coherent_dma):
gen_args.append("--coherent-dma")
gen_args.append(f"--cpu-count={VexRiscvSMP.cpu_count}")
gen_args.append(f"--ibus-width={VexRiscvSMP.icache_width}")
gen_args.append(f"--dbus-width={VexRiscvSMP.dcache_width}")
gen_args.append(f"--dcache-size={VexRiscvSMP.dcache_size}")
gen_args.append(f"--icache-size={VexRiscvSMP.icache_size}")
gen_args.append(f"--dcache-ways={VexRiscvSMP.dcache_ways}")
gen_args.append(f"--icache-ways={VexRiscvSMP.icache_ways}")
gen_args.append(f"--litedram-width={VexRiscvSMP.litedram_width}")
gen_args.append(f"--netlist-name={VexRiscvSMP.cluster_name}")
gen_args.append(f"--netlist-directory={vdir}")
cmd = 'cd {path} && sbt "runMain vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen {args}"'.format(path=os.path.join(vdir, "ext", "VexRiscv"), args=" ".join(gen_args))
os.system(cmd)
def copy_cpu_variant_if_needed(variant):
if variant in core.CPU_VARIANTS:
cpu_filename = core.CPU_VARIANTS[variant] + ".v"
vdir = get_data_mod("cpu", "vexriscv").data_location
fullpath = os.path.join(vdir, cpu_filename)
cfu_root = os.environ.get('CFU_ROOT')
custom_dir = os.path.join(cfu_root, "soc", "vexriscv")
custom_cpu = os.path.join(custom_dir, cpu_filename)
# always copy to ensure the most up-to-date version is used
if os.path.exists(custom_cpu):
print(f"Found and copied \"{custom_cpu}\".")
copyfile(custom_cpu, fullpath)
else:
if not os.path.exists(fullpath):
print(f"Couldn't find \"{fullpath}\".")
print(f"Couldn't find \"{custom_cpu}\".")
else:
print(f"Variant \"{variant}\" not known.")
def add_sources(platform, variant="standard"):
vdir = get_data_mod("cpu", "blackparrot").data_location
bp_litex = os.path.join(vdir, "bp_litex")
filename = os.path.join(bp_litex, {
"standard": "flist.fpga",
"sim": "flist.verilator"
}[variant])
with open(filename) as openfileobject:
for line in openfileobject:
temp = line
if (temp[0] == '/' and temp[1] == '/'):
continue
elif ("+incdir+" in temp):
s1 = line.find('$')
vdir = os.path.expandvars(line[s1:]).strip()
platform.add_verilog_include_path(vdir)
elif (temp[0] == '$'):
vdir = os.path.expandvars(line).strip()
platform.add_source(vdir, "systemverilog")
elif (temp[0] == '/'):
assert ("No support for absolute path for now")
def add_sources(self, platform):
vdir = get_data_mod("cpu", "naxriscv").data_location
print(f"NaxRiscv netlist : {self.netlist_name}")
if not os.path.exists(os.path.join(vdir, self.netlist_name + ".v")):
self.generate_netlist(self.reset_address)
# Add RAM.
# By default, use Generic RAM implementation.
ram_filename = "Ram_1w_1rs_Generic.v"
# On Altera/Intel platforms, use specific implementation.
from litex.build.altera import AlteraPlatform
if isinstance(platform, AlteraPlatform):
ram_filename = "Ram_1w_1rs_Intel.v"
# On Efinix platforms, use specific implementation.
from litex.build.efinix import EfinixPlatform
if isinstance(platform, EfinixPlatform):
ram_filename = "Ram_1w_1rs_Efinix.v"
platform.add_source(os.path.join(vdir, ram_filename), "verilog")
# Add Cluster.
platform.add_source(os.path.join(vdir, self.netlist_name + ".v"),
"verilog")
