def __init__(self, sys_clk_freq=int(50e6), with_video_terminal=False, **kwargs):
self.platform = platform = deca.Platform()
# Defaults to JTAG-UART since no hardware UART.
if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "jtag_atlantic"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Terasic DECA",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = self.crg = _CRG(platform, sys_clk_freq, with_usb_pll=False)
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoDVIPHY(platform.request("hdmi"), clock_domain="hdmi")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_uartbone=False, with_jtagbone=False, with_video_terminal=False,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50",
eth_dynamic_ip=False,
**kwargs):
self.platform = platform = deca.Platform()
# Defaults to JTAG-UART since no hardware UART.
real_uart_name = kwargs["uart_name"]
if real_uart_name == "serial":
if with_jtagbone:
kwargs["uart_name"] = "crossover"
else:
kwargs["uart_name"] = "jtag_uart"
if with_uartbone:
kwargs["uart_name"] = "crossover"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Terasic DECA",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = self.crg = _CRG(platform, sys_clk_freq, with_usb_pll=False)
# UARTbone ---------------------------------------------------------------------------------
if with_uartbone:
self.add_uartbone(name=real_uart_name, baudrate=kwargs["uart_baudrate"])
# JTAGbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.platform.toolchain.additional_sdc_commands += [
'create_clock -name eth_rx_clk -period 40.0 [get_ports {eth_clocks_rx}]',
'create_clock -name eth_tx_clk -period 40.0 [get_ports {eth_clocks_tx}]',
'set_false_path -from [get_clocks {sys_clk}] -to [get_clocks {eth_rx_clk}]',
'set_false_path -from [get_clocks {sys_clk}] -to [get_clocks {eth_tx_clk}]',
'set_false_path -from [get_clocks {eth_rx_clk}] -to [get_clocks {eth_tx_clk}]',
]
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoDVIPHY(platform.request("hdmi"), clock_domain="hdmi")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self, sys_clk_freq=int(50e6), with_vga=False, **kwargs):
platform = deca.Platform()
# Defaults to UART over JTAG because no hardware uart is on the board
if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "jtag_atlantic"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on DECA",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(50e6),
with_video_terminal=False,
sdram_rate="1:2",
mister_sdram=None,
**kwargs):
self.platform = platform = deca.Platform()
if mister_sdram != None:
platform.add_extension([
# MiSTer SDRAM (via GPIO expansion board on P8).
("sdram_clock", 0, Pins("P8:26"), IOStandard("3.3-V LVTTL")),
(
"sdram",
0,
Subsignal(
"a",
Pins("P8:43 P8:44 P8:45 P8:46 P8:34 P8:31 P8:32 P8:29",
"P8:30 P8:27 P8:42 P8:28 P8:25")),
Subsignal("ba", Pins("P8:40 P8:41")),
Subsignal("cs_n", Pins("P8:39")),
Subsignal(
"cke",
Pins("P8:18")), # CKE not connected on XS 2.2/2.4.
Subsignal("ras_n", Pins("P8:38")),
Subsignal("cas_n", Pins("P8:37")),
Subsignal("we_n", Pins("P8:33")),
Subsignal(
"dq",
Pins(
"P8:7 P8:8 P8:9 P8:10 P8:11 P8:12 P8:13 P8:14",
"P8:24 P8:23 P8:22 P8:21 P8:20 P8:19 P8:15 P8:16"),
),
Subsignal("dm", Pins("P8:35 P8:36")
), # DQML/DQMH not connected on XS 2.2/2.4
IOStandard("3.3-V LVTTL"),
Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
)
])
# Defaults to JTAG-UART since no hardware UART.
if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "jtag_atlantic"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Terasic DECA",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = self.crg = _CRG(platform,
sys_clk_freq,
with_usb_pll=False,
with_sdram=mister_sdram != None,
sdram_rate=sdram_rate,
with_video_terminal=False)
# SDR SDRAM --------------------------------------------------------------------------------
if mister_sdram is not None:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
sdrphy_mod = {
"xs_v22": W9825G6KH6,
"xs_v24": AS4C32M16
}[mister_sdram]
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=sdrphy_mod(sys_clk_freq, sdram_rate),
l2_cache_size=kwargs.get("l2_size", 8192))
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoDVIPHY(platform.request("hdmi"),
clock_domain="hdmi")
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="hdmi")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)