def __init__(self, revision="0.2", device="25F", sdram_device="MT41K64M16", sys_clk_freq=int(48e6), toolchain="trellis", **kwargs): platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain) # Serial ----------------------------------------------------------------------------------- if kwargs["uart_name"] == "usb_acm": # FIXME: do proper install of ValentyUSB. os.system("git clone https://github.com/gregdavill/valentyusb -b hw_cdc_eptri") sys.path.append("valentyusb") else: platform.add_extension(orangecrab.feather_serial) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on OrangeCrab", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: available_sdram_modules = { "MT41K64M16": MT41K64M16, "MT41K128M16": MT41K128M16, "MT41K256M16": MT41K256M16, "MT41K512M16": MT41K512M16, } sdram_module = available_sdram_modules.get(sdram_device) ddram_pads = platform.request("ddram") self.submodules.ddrphy = ECP5DDRPHY( pads = ddram_pads, sys_clk_freq = sys_clk_freq) self.ddrphy.settings.rtt_nom = "disabled" self.add_csr("ddrphy") if hasattr(ddram_pads, "vccio"): self.comb += ddram_pads.vccio.eq(0b111111) if hasattr(ddram_pads, "gnd"): self.comb += ddram_pads.gnd.eq(0) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy = self.ddrphy, module = sdram_module(sys_clk_freq, "1:2"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(48e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs): platform = orangecrab.Platform(toolchain=toolchain) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=integrated_rom_size, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_constant("ECP5DDRPHY", None) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) sdram_module = MT41K64M16(sys_clk_freq, "1:2") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs): platform = orangecrab.Platform(toolchain=toolchain) # SoCCore ----------------------------------------------------------------_----------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_constant("ECP5DDRPHY", None) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K64M16(sys_clk_freq, "1:2"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True)
def __init__(self, revision="0.2", device="25F", sdram_device="MT41K64M16", sys_clk_freq=int(48e6), toolchain="trellis", with_led_chaser=True, **kwargs): platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain) # Serial ----------------------------------------------------------------------------------- if kwargs["uart_name"] in ["serial", "usb_acm"]: kwargs["uart_name"] = "usb_acm" # Defaults to USB ACM through ValentyUSB. os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri") sys.path.append("valentyusb") # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on OrangeCrab", **kwargs) # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: available_sdram_modules = { "MT41K64M16": MT41K64M16, "MT41K128M16": MT41K128M16, "MT41K256M16": MT41K256M16, "MT41K512M16": MT41K512M16, } sdram_module = available_sdram_modules.get(sdram_device) ddram_pads = platform.request("ddram") self.submodules.ddrphy = ECP5DDRPHY( pads = ddram_pads, sys_clk_freq = sys_clk_freq, cmd_delay = 0 if sys_clk_freq > 64e6 else 100) self.ddrphy.settings.rtt_nom = "disabled" if hasattr(ddram_pads, "vccio"): self.comb += ddram_pads.vccio.eq(0b111111) if hasattr(ddram_pads, "gnd"): self.comb += ddram_pads.gnd.eq(0) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy = self.ddrphy, module = sdram_module(sys_clk_freq, "1:2"), l2_cache_size = kwargs.get("l2_size", 8192) ) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, revision="0.2", device="25F", sdram_device="MT41K64M16", sys_clk_freq=int(48e6), toolchain="trellis", **kwargs): platform = orangecrab.Platform(revision=revision, device=device, toolchain=toolchain) # Serial ----------------------------------------------------------------------------------- platform.add_extension(orangecrab.feather_serial) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: available_sdram_modules = { 'MT41K64M16': MT41K64M16, 'MT41K128M16': MT41K128M16, 'MT41K256M16': MT41K256M16, # 'MT41K512M16': MT41K512M16 } sdram_module = available_sdram_modules.get(sdram_device) self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.add_sdram("sdram", phy=self.ddrphy, module=sdram_module(sys_clk_freq, "1:2"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True)
def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs): # Board Revision --------------------------------------------------------------------------- revision = kwargs.get("revision", "0.2") device = kwargs.get("device", "25F") platform = orangecrab.Platform(revision=revision, device=device, toolchain=toolchain) platform.add_extension(extras) # Disconnect Serial Debug (Stub required so BIOS is kept happy) kwargs['uart_name'] = "stream" # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, csr_data_width=32, **kwargs) # connect UART stream to NULL self.comb += self.uart.source.ready.eq(1) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = crg = CRG(platform, sys_clk_freq, with_usb_pll=True) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: available_sdram_modules = { "MT41K64M16": MT41K64M16, "MT41K128M16": MT41K128M16, "MT41K256M16": MT41K256M16, "MT41K512M16": MT41K512M16, } sdram_module = available_sdram_modules.get( kwargs.get("sdram_device", "MT41K64M16")) ddram_pads = platform.request("ddram") self.submodules.ddrphy = ECP5DDRPHY(pads=ddram_pads, sys_clk_freq=sys_clk_freq) self.ddrphy.settings.rtt_nom = "disabled" self.add_csr("ddrphy") if hasattr(ddram_pads, "vccio"): self.comb += ddram_pads.vccio.eq(0b111111) if hasattr(ddram_pads, "gnd"): self.comb += ddram_pads.gnd.eq(0) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy=self.ddrphy, module=sdram_module(sys_clk_freq, "1:2"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # RGB LED self.submodules.rgb = RGB(platform.request("rgb_led", 0)) #self.submodules.gpio = GPIOTristateCustom(platform.request("gpio", 0)) self.submodules.gpio = IOPort(platform.request("gpio", 0)) try: self.submodules.button = GPIOIn(platform.request("usr_btn")) except: ... # Analog Mux #self.submodules.asense = AnalogSense(platform.request("analog")) # drive PROGRAMN HIGH self.comb += platform.request("rst_n").eq(1) # The litex SPI module supports memory-mapped reads, as well as a bit-banged mode # for doing writes. spi_pads = platform.request("spiflash4x") self.submodules.lxspi = spi_flash.SpiFlashDualQuad(spi_pads, dummy=6, endianness="little") self.lxspi.add_clk_primitive(platform.device) self.register_mem("spiflash", self.mem_map["spiflash"], self.lxspi.bus, size=16 * 1024 * 1024) # Attach USB to a seperate CSR bus that's decoupled from our CPU clock usb_pads = platform.request("usb") usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup) self.submodules.usb0 = CSRClockDomainWrapper(usb_iobuf) self.comb += self.cpu.interrupt[self.interrupt_map['usb']].eq( self.usb0.irq) from litex.soc.integration.soc_core import SoCRegion self.bus.add_slave( 'usb', self.usb0.bus, SoCRegion(origin=0x90000000, size=0x1000, cached=False)) self.constants[ "FLASH_BOOT_ADDRESS"] = self.mem_map['spiflash'] + 0x00100000
def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs): # Board Revision --------------------------------------------------------------------------- revision = kwargs.get("revision", "0.2") device = kwargs.get("device", "25F") platform = orangecrab.Platform(revision=revision, device=device, toolchain=toolchain) # Serial ----------------------------------------------------------------------------------- #platform.add_extension(orangecrab.feather_serial) # USB hardware Abstract Control Model. kwargs['uart_name'] = "usb_acm" # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, csr_data_width=32, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = crg = CRG(platform, sys_clk_freq, with_usb_pll=True) # DDR3 SDRAM ------------------------------------------------------------------------------- if 1: if not self.integrated_main_ram_size: available_sdram_modules = { 'MT41K64M16': MT41K64M16, 'MT41K128M16': MT41K128M16, 'MT41K256M16': MT41K256M16 } sdram_module = available_sdram_modules.get( kwargs.get("sdram_device", "MT41K64M16")) ddr_pads = platform.request("ddram") self.submodules.ddrphy = ECP5DDRPHY(ddr_pads, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_constant("ECP5DDRPHY") self.comb += crg.stop.eq(self.ddrphy.init.stop) self.comb += crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy=self.ddrphy, module=sdram_module(sys_clk_freq, "1:2"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Virtual power pins - suggested to reduce SSO noise self.comb += ddr_pads.vccio.eq(0b111111) self.comb += ddr_pads.gnd.eq(0) # Add extra pin definitions platform.add_extension(extras) # RGB LED led = platform.request("rgb_led", 0) self.submodules.gpio_led = GPIOTristate(Cat(led.r, led.g, led.b)) # i2c self.submodules.i2c = I2CMaster(platform.request("i2c")) # SDR processor self.submodules.sdr = sdr(platform.request("ad9203"), platform.request("pdm_out")) platform.add_source_dir('vsrc') # Controllable Self Reset reset_code = Signal(32, reset=0) self.submodules.self_reset = GPIOOut(reset_code) self.comb += platform.request("rst_n").eq(reset_code != 0xAA550001) self.submodules.button = GPIOIn(platform.request("usr_btn")) # The litex SPI module supports memory-mapped reads, as well as a bit-banged mode # for doing writes. spi_pads = platform.request("spiflash4x") self.submodules.lxspi = spi_flash.SpiFlashDualQuad(spi_pads, dummy=6, endianness="little") self.lxspi.add_clk_primitive(platform.device) self.register_mem("spiflash", self.mem_map["spiflash"], self.lxspi.bus, size=16 * 1024 * 1024) # Add GIT repo to the firmware git_rev_cmd = subprocess.Popen(["git", "rev-parse", "--short", "HEAD"], stdout=subprocess.PIPE, stderr=subprocess.PIPE) (git_stdout, _) = git_rev_cmd.communicate() self.add_constant('REPO_GIT_SHA1', git_stdout.decode('ascii').strip('\n'))
def __init__(self, revision="0.2", device="25F", sdram_device="MT41K64M16", sys_clk_freq=int(48e6), toolchain="trellis", **kwargs): platform = orangecrab.Platform(revision=revision, device=device, toolchain=toolchain) # Serial ----------------------------------------------------------------------------------- if kwargs["uart_name"] == "usb_acm": sys.path.append("valentyusb") else: platform.add_extension(orangecrab.feather_serial) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on OrangeCrab", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: available_sdram_modules = { "MT41K64M16": MT41K64M16, "MT41K128M16": MT41K128M16, "MT41K256M16": MT41K256M16, "MT41K512M16": MT41K512M16, } sdram_module = available_sdram_modules.get(sdram_device) ddram_pads = platform.request("ddram") self.submodules.ddrphy = ECP5DDRPHY(pads=ddram_pads, sys_clk_freq=sys_clk_freq) self.ddrphy.settings.rtt_nom = "disabled" self.add_csr("ddrphy") if hasattr(ddram_pads, "vccio"): self.comb += ddram_pads.vccio.eq(0b111111) if hasattr(ddram_pads, "gnd"): self.comb += ddram_pads.gnd.eq(0) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy=self.ddrphy, module=sdram_module(sys_clk_freq, "1:2"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds") # my peripheral thing platform.add_extension([("c2", 0, Subsignal("c2ck", Pins("GPIO:0"), IOStandard("LVCMOS33")), Subsignal("c2d", Pins("GPIO:1"), IOStandard("LVCMOS33")), Subsignal("power", Pins("GPIO:13"), IOStandard("LVCMOS33")))]) self.submodules.c2 = c2.C2Interface(platform.request("c2")) self.add_csr("c2")