def main(): parser = argparse.ArgumentParser(description="LiteSATA bench on XCU1525") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)") parser.add_argument("--gen", default="3", help="SATA Gen: 1, 2 or 3 (default)") parser.add_argument("--connector", default="qsfp", help="SATA Connector: qsfp (default) or pcie") parser.add_argument("--with-analyzer", action="store_true", help="Add LiteScope Analyzer") args = parser.parse_args() platform = xcu1525.Platform() platform.add_extension(_sata_io) soc = SATATestSoC(platform, args.connector, "gen" + args.gen, with_analyzer=args.with_analyzer) builder = Builder(soc, csr_csv="csr.csv") builder.build(run=args.build) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream( os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main(): parser = argparse.ArgumentParser(description="LitePCIe SoC on XCU1525") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)") parser.add_argument("--speed", default="gen2", help="PCIe speed: gen2 (default) or gen3") parser.add_argument("--nlanes", default=4, help="PCIe lanes: 4 (default) or 8") args = parser.parse_args() platform = xcu1525.Platform() soc = LitePCIeSoC(platform, speed=args.speed, nlanes=int(args.nlanes)) builder = Builder(soc, output_dir="build/xcu1525", csr_csv="csr.csv") builder.build(build_name="xcu1525", run=args.build) if args.driver: generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream( os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def __init__(self, sys_clk_freq=int(125e6)): platform = xcu1525.Platform() platform.add_extension(_qsfp_io) # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, ident="LiteEth bench on XCU1525", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = USP_1000BASEX(self.crg.cd_eth.clk, data_pads=self.platform.request( "qsfp", 0), sys_clk_freq=self.clk_freq) self.comb += self.platform.request("qsfp_fs").eq(0b01) self.add_etherbone(phy=self.ethphy, buffer_depth=255) # SRAM ------------------------------------------------------------------------------------- self.add_ram("sram", 0x20000000, 0x1000) # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), channel=0, with_bist=False, with_analyzer=False): platform = xcu1525.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, ident="LiteDRAM bench on XCU1525", ident_version=True, integrated_rom_size=0x10000, integrated_rom_mode="rw", uart_name=uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, channel) # DDR4 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request( "ddram", channel), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6) self.add_sdram("sdram", phy=self.ddrphy, module=MT40A512M8(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=0x40000000, with_bist=with_bist) # Workaround for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") # UARTBone --------------------------------------------------------------------------------- if uart != "serial": self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") # Analyzer --------------------------------------------------------------------------------- if with_analyzer: from litescope import LiteScopeAnalyzer analyzer_signals = [self.ddrphy.dfi] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, depth=256, clock_domain="sys", csr_csv="analyzer.csv") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), channel=0, with_bist=False): platform = xcu1525.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x10000, integrated_rom_mode="rw", csr_data_width=32, uart_name=uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, channel) self.add_csr("crg") # DDR4 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request( "ddram", channel), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6) self.add_csr("ddrphy") self.add_sdram( "sdram", phy=self.ddrphy, module=MT40A512M8(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=0x40000000, with_bist=with_bist, ) # Workaround for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") # UARTBone --------------------------------------------------------------------------------- if uart != "serial": self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def main(): parser = argparse.ArgumentParser(description="LiteICLink transceiver example on XCU1525") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)") parser.add_argument("--connector", default="qsfp0", help="Connector: qsfp0 (default) or qsfp1") parser.add_argument("--linerate", default="2.5e9", help="Linerate (default: 2.5e9)") parser.add_argument("--pll", default="cpll", help="PLL: cpll (default) or qpll") args = parser.parse_args() platform = xcu1525.Platform() platform.add_extension(_transceiver_io) soc = GTYTestSoC(platform, connector = args.connector, linerate = float(args.linerate), use_qpll = args.pll == "qpll" ) builder = Builder(soc, csr_csv="csr.csv") builder.build(run=args.build) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def __init__(self, sys_clk_freq=int(125e6), ddram_channel=0, with_led_chaser=True, with_pcie=False, with_sata=False, **kwargs): platform = xcu1525.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on XCU1525", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, ddram_channel) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( pads=platform.request("ddram", ddram_channel), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6) self.add_sdram("sdram", phy=self.ddrphy, module=MT40A512M8(sys_clk_freq, "1:4"), size=0x40000000, l2_cache_size=kwargs.get("l2_size", 8192)) # Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # IOs _sata_io = [ # SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter ( "qsfp2sata", 0, Subsignal("tx_p", Pins("N9")), Subsignal("tx_n", Pins("N8")), Subsignal("rx_p", Pins("N4")), Subsignal("rx_n", Pins("N3")), ), ] platform.add_extension(_sata_io) # RefClk, Generate 150MHz from PLL. self.clock_domains.cd_sata_refclk = ClockDomain() self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6) sata_refclk = ClockSignal("sata_refclk") # PHY self.submodules.sata_phy = LiteSATAPHY( platform.device, refclk=sata_refclk, pads=platform.request("qsfp2sata"), gen="gen2", clk_freq=sys_clk_freq, data_width=16) # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(125e6), ddram_channel=0, with_pcie=False, **kwargs): platform = xcu1525.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on XCU1525", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( pads=platform.request("ddram", ddram_channel), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6, cmd_latency=1) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT40A512M8(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") # PCIe ------------------------------------------------------------------------------------- if with_pcie: # PHY self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint( self.pcie_phy, max_pending_requests=8) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma0") self.add_constant("DMA_CHANNELS", 1) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")