def test_bypassed_basic():
run_test_vector_sim(RegisterFile(8, 4, 1, 1, True, True), [
('read_addr[0] read_data[0]* write_addr[0] write_data[0] write_call[0]'
),
(0, 255, 0, 255, 1),
(0, 255, 0, 0, 0),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_inc_multi():
run_test_vector_sim(WrapIncVar(2, 4, True, 2), [
('inc_in inc_ops inc_out*'),
(0, 0, 0),
(0, 1, 1),
(0, 2, 2),
(2, 2, 0),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_cl_adapter():
run_test_vector_sim(wrap_to_rtl(MuxFL(Bits(4), 4)), [
('mux_in_[0] mux_in_[1] mux_in_[2] mux_in_[3] mux_select mux_out*'),
(0b0001, 0b0010, 0b0100, 0b1000, 0b00, 0b0001),
(0b0001, 0b0010, 0b0100, 0b1000, 0b01, 0b0010),
(0b0001, 0b0010, 0b0100, 0b1000, 0b10, 0b0100),
(0b0001, 0b0010, 0b0100, 0b1000, 0b11, 0b1000),
],
dump_vcd=None,
test_verilog=False)
def test_basic():
run_test_vector_sim(Mux(Bits(4), 4), [
('mux_in_[0] mux_in_[1] mux_in_[2] mux_in_[3] mux_select mux_out*'),
(0b0001, 0b0010, 0b0100, 0b1000, 0b00, 0b0001),
(0b0001, 0b0010, 0b0100, 0b1000, 0b01, 0b0010),
(0b0001, 0b0010, 0b0100, 0b1000, 0b10, 0b0100),
(0b0001, 0b0010, 0b0100, 0b1000, 0b11, 0b1000),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_basic():
run_test_vector_sim(OneHotEncoder(4), [
('encode_number encode_onehot*'),
(0, 0b0001),
(1, 0b0010),
(2, 0b0100),
(3, 0b1000),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_inc_basic():
run_test_vector_sim(WrapInc(2, 4, True), [
('inc_in inc_out*'),
(0, 1),
(1, 2),
(2, 3),
(3, 0),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_basic():
run_test_vector_sim(Packer(1, 4), [
('pack_in_[0] pack_in_[1] pack_in_[2] pack_in_[3] pack_packed'),
(0, 0, 0, 0, 0b0000),
(0, 1, 1, 1, 0b0111),
(1, 1, 1, 1, 0b1111),
(1, 0, 1, 0, 0b1010),
(1, 1, 1, 0, 0b1110),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_bypass():
run_test_vector_sim(FreeList(2, 1, 1, True, False), [
('alloc_call[0] alloc_rdy[0]* alloc_index[0]* alloc_mask[0]* free_call[0] free_index[0]'
),
(1, 1, 0, 0b0001, 0, 0),
(1, 1, 1, 0b0010, 0, 0),
(1, 1, 1, 0b0010, 1, 1),
(1, 1, 0, 0b0001, 1, 0),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_reverse_free_order():
run_test_vector_sim(FreeList(2, 1, 1, False, False), [
('alloc_call[0] alloc_rdy[0]* alloc_index[0]* alloc_mask[0]* free_call[0] free_index[0]'
),
(1, 1, 0, 0b0001, 0, 0),
(1, 1, 1, 0b0010, 0, 0),
(0, 0, '?', '?', 1, 1),
(1, 1, 1, 0b0010, 0, 0),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_release():
run_test_vector_sim(FreeList(4, 1, 1, False, False), [
('alloc_call[0] alloc_rdy[0]* alloc_index[0]* alloc_mask[0]* free_call[0] free_index[0] release_call release_mask'
),
(1, 1, 0, 0b0001, 0, 0, 0, 0b0000),
(1, 1, 1, 0b0010, 0, 0, 0, 0b0000),
(1, 1, 2, 0b0100, 0, 0, 1, 0b0011),
(1, 1, 0, 0b0001, 1, 1, 0, 0b0000),
(1, 1, 1, 0b0010, 1, 0, 0, 0b0000),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_used_initial():
run_test_vector_sim(FreeList(4, 1, 1, False, False, 2), [
('alloc_call[0] alloc_rdy[0]* alloc_index[0]* alloc_mask[0]* free_call[0] free_index[0]'
),
(1, 1, 2, 0b0100, 0, 0),
(1, 1, 3, 0b1000, 0, 0),
(0, 0, '?', '?', 1, 0),
(1, 1, 0, 0b0001, 0, 0),
(0, 0, '?', '?', 0, 0),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_dump_basic():
run_test_vector_sim(RegisterFile(8, 2, 1, 1, False, False), [
('read_addr[0] read_data[0]* write_addr[0] write_data[0] write_call[0] dump_out[0]* dump_out[1]* set_in_[0] set_in_[1] set_call'
),
(0, 0, 0, 5, 1, '?', '?', 0, 0, 0),
(0, 5, 1, 3, 1, '?', '?', 0, 0, 0),
(0, 5, 0, 0, 0, 5, 3, 0, 0, 0),
(0, 5, 0, 0, 0, 5, 3, 4, 2, 1),
(0, 4, 0, 0, 0, 4, 2, 0, 0, 0),
(0, 4, 0, 5, 1, 4, 2, 4, 2, 1),
(0, 4, 0, 0, 0, 4, 2, 0, 0, 0),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_cl_adapter():
run_test_vector_sim(wrap_to_rtl(FreeListFL(4, 1, 1, False, False)), [
('alloc_call[0] alloc_rdy[0]* alloc_index[0]* alloc_mask[0]* free_call[0] free_index[0]'
),
(1, 1, 0, 0b0001, 0, 0),
(1, 1, 1, 0b0010, 0, 0),
(0, 1, '?', '?', 1, 0),
(1, 1, 0, 0b0001, 0, 0),
(1, 1, 2, 0b0100, 0, 0),
(1, 1, 3, 0b1000, 0, 0),
(0, 0, '?', '?', 1, 1),
(1, 1, 1, 0b0010, 0, 0),
],
dump_vcd=None,
test_verilog=False)
def test_basic():
run_test_vector_sim(
PriorityDecoder(4), [
('decode_signal decode_valid* decode_decoded*'),
(0b0000, 0, '?'),
(0b0001, 1, 0),
(0b0010, 1, 1),
(0b0100, 1, 2),
(0b1000, 1, 3),
(0b1111, 1, 0),
(0b1110, 1, 1),
(0b1100, 1, 2),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_basic():
run_test_vector_sim(SnapshottingFreeList(4, 1, 1, 4), [
('alloc_call[0] alloc_rdy[0]* alloc_index[0]* alloc_mask[0]* free_call[0] free_index[0] set_call'
),
(1, 1, 0, 0b0001, 0, 0, 0),
(1, 1, 1, 0b0010, 0, 0, 0),
(0, 1, '?', '?', 1, 0, 0),
(1, 1, 0, 0b0001, 0, 0, 0),
(1, 1, 2, 0b0100, 0, 0, 0),
(1, 1, 3, 0b1000, 0, 0, 0),
(0, 0, '?', '?', 1, 1, 0),
(1, 1, 1, 0b0010, 0, 0, 0),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_snapshot_write_bypassed():
run_test_vector_sim(
SnapshottingRegisterFile(8, 4, 1, 1, False, True, 1),
[
('read_addr[0] read_data[0]* write_addr[0] write_data[0] write_call[0] snapshot_call snapshot_target_id restore_call restore_source_id'
),
(0, 0, 0, 8, 1, 0, 0, 0, 0),
(0, 8, 2, 3, 1, 0, 0, 0, 0),
(0, 8, 2, 4, 1, 1, 0, 0,
0), # save a snapshot into slot 0 (occurs after write)
(0, 8, 0, 7, 1, 0, 0, 0, 0),
(2, 4, 0, 0, 0, 0, 0, 1, 0), # restore the snapshot
(2, 4, 0, 0, 0, 0, 0, 0, 0),
(0, 8, 0, 0, 0, 0, 0, 0, 0),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_simple_revert():
run_test_vector_sim(
SnapshottingFreeList(4, 1, 1, 4),
[
('alloc_call[0] alloc_rdy[0]* alloc_index[0]* alloc_mask[0]* free_call[0] free_index[0] reset_alloc_tracking_call reset_alloc_tracking_target_id revert_allocs_call revert_allocs_source_id set_call'
),
(1, 1, 0, 0b0001, 0, 0, 1, 0, 0, 0, 0),
(1, 1, 1, 0b0010, 0, 0, 0, 0, 0, 0, 0),
(1, 1, 2, 0b0100, 0, 0, 0, 0, 0, 0, 0),
(1, 1, 3, 0b1000, 0, 0, 0, 0, 0, 0, 0),
(0, 0, '?', '?', 0, 0, 0, 0, 1, 0, 0), # free 1, 2, and 3 (not 0)
(1, 1, 1, 0b0010, 0, 0, 0, 0, 0, 0, 0),
(1, 1, 2, 0b0100, 0, 0, 0, 0, 0, 0, 0),
(1, 1, 3, 0b1000, 0, 0, 0, 0, 0, 0, 0),
(0, 0, '?', '?', 0, 0, 0, 0, 0, 0, 0), # should be full
],
dump_vcd=None,
test_verilog=test_verilog)
def test_basic():
run_test_vector_sim(
SnapshottingRegisterFile(64, 32, 2, 1, False, False, 1),
[
('read_addr[0] read_data[0]* write_addr[0] write_data[0] write_call[0] snapshot_call snapshot_target_id restore_call restore_source_id'
),
(0, 0, 0, 8, 1, 0, 0, 0, 0),
(0, 8, 2, 3, 1, 0, 0, 0, 0),
(2, 3, 0, 0, 0, 0, 0, 0, 0),
(2, 3, 0, 0, 0, 1, 0, 0, 0), # save a snapshot into slot 0
(0, 8, 0, 7, 1, 0, 0, 0, 0),
(0, 7, 2, 4, 1, 0, 0, 0, 0),
(2, 4, 0, 0, 0, 0, 0, 0, 0),
(2, 4, 0, 0, 0, 0, 0, 1, 0), # restore the snapshot
(0, 8, 2, 3, 1, 0, 0, 0, 0),
(2, 3, 0, 0, 0, 0, 0, 0, 0),
],
dump_vcd=None,
test_verilog=test_verilog)
def test_basic():
run_test_vector_sim(
RenameTable(2, 4, 2, 1, 1, True, [0, 0]),
[
('lookup_areg[0] lookup_preg[0]* lookup_areg[1] lookup_preg[1]* update_call[0] update_areg[0] update_preg[0] snapshot_call snapshot_target_id restore_call restore_source_id'
),
(0, 3, 1, 0, 1, 1, 1, 0, 0, 0,
0), # read r0 and r1 as ZERO_TAG and p0, write r1 as p1
(0, 3, 1, 1, 0, 0, 0, 0, 0, 0,
0), # read r0 and r1 as ZERO_TAG and p1, no write
(0, 3, 1, 1, 1, 1, 2, 1, 0, 0,
0), # read r0 and r1 as ZERO_TAG and p1, write r1 as p2, snapshot
(0, 3, 1, 2, 1, 1, 0, 0, 0, 0,
0), # read r0 and r1 as ZERO_TAG and p2, write r1 as p0, snapshot
(0, 3, 1, 0, 0, 0, 0, 0, 0, 1,
0), # read r0 and r1 as ZERO_TAG and p0, restoring snapshot
(0, 3, 1, 2, 0, 0, 0, 0, 0, 0,
0), # read r0 and r1 as ZERO_TAG and p2
],
dump_vcd=None,
test_verilog=test_verilog)
