#dummy = False dummy = True # This script is also used to test the DC2512 in production. Test pattern is # an 18-bit counter applied to the data bus. Linduino / QuikEval header must # have a 32-bit delay between MOSI and MISO - an LTC2668 demo board (DC2025) # can be used for this purpose. # MUX selection bitfields ADC_DATA = 0x00000000 FILTERED_ADC_DATA = 0x00000001 RAMP_DATA = 0x00000004 start_time = time.time() print('Starting client') client = MemClient(host=HOST) #Read FPGA type and revision. This inherently checks the reg_read function # (see type_rev_check function definition) # Arguments are client (of course), expected FPGA load type, and minimum revision if demo_board == 2512: type_rev_check(client, 0x0001, 0x0104) elif demo_board == 2390: type_rev_check(client, 0xABCD, 0x1246) # If we're using a DC2390, need to configure clocks LTC6954_configure(client) # And configure sample rate. client.reg_write(SYSTEM_CLOCK_BASE, 99) # 50MHz / (99 + 1) = 500ksps print('Okay, now lets blink some lights and run some tests!!')
############################################################################### # Main program ############################################################################### print "\n/////////////////////////////////////" print "// LTC2512 Trace Filter Shape Demo //" print "/////////////////////////////////////" raw_input("\nPlease set jumper 10 and 11 to 1, \nthen hit enter") # Get the host from the command line argument. Can be numeric or hostname. HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1' print '\nStarting client' client = MemClient(host=HOST) #Read FPGA type and revision rev_id = client.reg_read(REV_ID_BASE) type_id = rev_id & 0x0000FFFF rev = (rev_id >> 16) & 0x0000FFFF print 'FPGA load type ID: %04X' % type_id print 'FPGA load revision: %04X' % rev start_time = time.time() print("Setting up system parameters.\n") client.reg_write(SYSTEM_CLOCK_BASE, ((LUT_NCO_DIVIDER << 16) | SYSTEM_CLOCK_DIVIDER)) client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES)
CHANNEL = ADC_B_CAPTURE N = 7 #Number of samples to average (LTC2380-24) nco_word_width = 32 master_clock = 50000000 bin_number = 522 # Number of cycles over the time record sample_rate = master_clock / (SYSTEM_CLOCK_DIVIDER + 1 ) # 250ksps for 50M clock, 200 clocks per sample cycles_per_sample = float(bin_number) / float(NUM_SAMPLES) cycles_per_dac_sample = cycles_per_sample / (SYSTEM_CLOCK_DIVIDER + 1) tuning_word = int(cycles_per_dac_sample * 2**nco_word_width) print("Tuning Word:" + str(tuning_word)) print('Starting client') client = MemClient(host=HOST) #First thing's First!! Configure clocks... LTC6954_configure(client) #Read FPGA type and revision rev_id = client.reg_read(REV_ID_BASE) type_id = rev_id & 0x0000FFFF rev = (rev_id >> 16) & 0x0000FFFF print('FPGA load type ID: %04X' % type_id) print('FPGA load revision: %04X' % rev) print("Setting up system parameters.\n") client.reg_write(SYSTEM_CLOCK_BASE, SYSTEM_CLOCK_DIVIDER) client.reg_write(SYSTEM_CLOCK_BASE, (LUT_NCO_DIVIDER << 16 | SYSTEM_CLOCK_DIVIDER)) client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES) client.reg_write(PID_KP_BASE, PID_KP)
filter_str = "SSINC 4096" filt = DC2390.LTC2500_SSINC_FILT df = DC2390.LTC2500_DF_4096 else: filter_str = "SINC 2048" filt = DC2390.LTC2500_SINC_FILT df = DC2390.LTC2500_DF_2048 # Keep track of start time start_time = time.time() # Get the host from the command line argument. Can be numeric or hostname. HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1' # Connect to the SoC client = MemClient(host=HOST) # Verify the FPGA bistream #-------------------------------------------------------------------------- #Read FPGA type and revision rev_id = client.reg_read(DC2390.REV_ID_BASE) type_id = rev_id & 0x0000FFFF rev = (rev_id >> 16) & 0x0000FFFF if (type_id != 0xABCD) or (rev != 0x1238): print "Wrong FPGA bitstream on the FPGA" print 'FPGA load type ID: %04X' % type_id print 'FPGA load revision: %04X' % rev else: print "Correct bitstream file found !!"
# Get the host from the command line argument. Can be numeric or hostname. # If no host given, assume local machine (such as the SoCkit board itself) HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1' # For example, if you're using the default fixed address that the SoCkit assigns # itself if DHCP fails, you would run: # python DC2390_hello_world.py "192.168.1.231" # If you're running this script ON the sockit board itself, you would run: # python DC2390_hello_world.py # Now we create an instance of MemClient, called "client", pointing it at # the SoCkit's IP address. This is the "pipeline" that allows us to communicate. print('Starting client') client = MemClient(host=HOST) # First thing's First!! Unfortunately we can't even blink a light without first # Configuring the clocks, which are provided from a crystal oscillator and # LTC6954 clock distribution divider / driver LTC6954_configure(client) #Read FPGA type and revision rev_id = client.reg_read(REV_ID_BASE) type_id = rev_id & 0x0000FFFF rev = (rev_id >> 16) & 0x0000FFFF print ('FPGA load type ID: %04X' % type_id) print ('FPGA load revision: %04X' % rev) LUT_DIVIDER = 0xC000 # Let's start with half-depth... SYSTEM_CLOCK_DIVIDER = 1250
"4", "8", "16", "32", "64", "128", "256", "512", "1024", "2048", "4096", "8192", "16384" ] DF_VALS = [4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384] GAIN = "18" ############################################################################### # Main program ############################################################################### # Get the host from the command line argument. Can be numeric or hostname. HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1' print '\nStarting client' client = MemClient(host=HOST) #Read FPGA type and revision rev_id = client.reg_read(REV_ID_BASE) type_id = rev_id & 0x0000FFFF rev = (rev_id >> 16) & 0x0000FFFF print 'FPGA load type ID: %04X' % type_id print 'FPGA load revision: %04X' % rev start_time = time.time() print("Setting up system parameters.\n") client.reg_write(SYSTEM_CLOCK_BASE, ((LUT_NCO_DIVIDER << 16) | SYSTEM_CLOCK_DIVIDER)) client.reg_write(NUM_SAMPLES_BASE, NUM_NYQ_SAMPLES)
# Limit the range if code < 0.0: code = 0.0 if code > 262143.0: code = 262143.0 return int(code) # Convert to integer if __name__ == "__main__": # Get the host from the command line argument. Can be numeric or hostname. HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1' # Connect to the SoC client = MemClient(host=HOST) # Verify the FPGA bistream #Read FPGA type and revision rev_id = client.reg_read(DC2390.REV_ID_BASE) type_id = rev_id & 0x0000FFFF rev = (rev_id >> 16) & 0x0000FFFF if (type_id != 0xABCD) or (rev != 0x1238): print "Wrong FPGA bitstream on the FPGA" print 'FPGA load type ID: %04X' % type_id print 'FPGA load revision: %04X' % rev else: print "Correct bitstream file found !!" # Set the LTC695 to 50 MHz
# Get the host from the command line argument. Can be numeric or hostname. # If no host given, assume local machine (such as the SoCkit board itself) HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1' # For example, if you're using the default fixed address that the SoCkit assigns # itself if DHCP fails, you would run: # python DC2390_hello_world.py "192.168.1.231" # If you're running this script ON the sockit board itself, you would run: # python DC2390_hello_world.py # Now we create an instance of MemClient, called "client", pointing it at # the SoCkit's IP address. This is the "pipeline" that allows us to communicate. print('Starting client') client = MemClient(host=HOST) # First thing's First!! Unfortunately we can't even blink a light without first # Configuring the clocks, which are provided from a crystal oscillator and # LTC6954 clock distribution divider / driver # The following routines read and write registers in the FPGA. These can be # either read or write (or both), depending on the exact design. # But fundamentally, when reading or writing a register from a script such as # this one, you are reading or setting the state of a signal in the FPGA design. # The addresses of the registers we will be talking to are defined in # DC2390_functions.py, imported above. If you open it up, you will see these lines: # REV_ID_BASE = 0x10 LED_BASE = 0x40
#!/usr/bin/python # Example application for running tests on the Arrow SoCkit board # using the LT_soc_framework # This script tests all the dummy functions import sys from llt.common.mem_func_client_2 import MemClient # Get the host from the command line argument. Can be numeric or hostname. #HOST = sys.argv.pop() if len(sys.argv) == 2 else '127.0.0.1' HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1' print('Starting client\n') client = MemClient(host=HOST) # no need for any configuration verbose = True dummy = False error = 0 reg_address = 0x60 reg_value = 0xB7 mem_address = 0x88 mem_value = 0xB5 number_of_writes = 3 number_of_reads = 50 starting_address = reg_address reg_values = []
N = 7 #Number of samples to average (LTC2380-24) vfs = 10.0 # Full-scale voltage, VREF * 2 for LTC25xx family nco_word_width = 32 # A property of the NCO in the FPGA design master_clock = 50000000 # Relies on proper configuration of LTC6954 divider bin_number = 50 # Number of cycles over the time record for sine signal sample_rate = master_clock / (SYSTEM_CLOCK_DIVIDER + 1 ) # 250ksps for 50M clock, 200 clocks per sample cycles_per_sample = float(bin_number) / float(NUM_SAMPLES) cycles_per_dac_sample = cycles_per_sample / (SYSTEM_CLOCK_DIVIDER + 1) tuning_word = int(cycles_per_dac_sample * 2**nco_word_width) print("Tuning Word:" + str(tuning_word)) print('Starting client') client = MemClient(host=HOST) #First thing's First!! Configure clocks... LTC6954_configure(client, 0x04) #Read FPGA type and revision type_rev_check(client, 0xABCD, 0x1246) print("Setting up system parameters.\n") client.reg_write(SYSTEM_CLOCK_BASE, SYSTEM_CLOCK_DIVIDER) client.reg_write(SYSTEM_CLOCK_BASE, (LUT_NCO_DIVIDER << 16 | SYSTEM_CLOCK_DIVIDER)) client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES) client.reg_write(PID_KP_BASE, PID_KP) client.reg_write(PID_KI_BASE, PID_KI) client.reg_write(PID_KD_BASE, PID_KD) client.reg_write(PULSE_LOW_BASE, PULSE_LOW) client.reg_write(PULSE_HIGH_BASE, PULSE_HIGH)
save_pscope_data = False grab_filtered_data = False mem_bw_test = False bit_counter = False plot_data = False numbits = 16 NUM_SAMPLES = 2**17 # Twice through all 16 bits # MUX selection ADC_DATA = 0x00000000 FILTERED_ADC_DATA = 0x00000001 RAMP_DATA = 0x00000004 start_time = time.time(); print('Starting client') client = MemClient(host=HOST) #Read FPGA type and revision rev_id = client.reg_read(REV_ID_BASE) type_id = rev_id & 0x0000FFFF rev = (rev_id >> 16) & 0x0000FFFF print ('FPGA load type ID: %04X' % type_id) print ('FPGA load revision: %04X' % rev) if type_id != 0x0001: print("FPGA type is NOT 0x0001! Make sure you know what you're doing!") print ('Okay, now lets blink some lights and run some tests!!') client.reg_write(LED_BASE, 0x01) sleep(0.1) client.reg_write(LED_BASE, 0x00)
if ADC == 2512: if DF == 4: raw_input("\nPlease set SEL1, SEL0 jumpers to 0, 0 \nthen hit enter") elif DF == 8: raw_input("\nPlease set SEL1, SEL0 jumpers to 0, 1 \nthen hit enter") elif DF == 16: raw_input("\n\nPlease set SEL1, SEL0 jumpers to 1, 0 \nthen hit enter") else: raw_input("\n\nPlease set SEL1, SEL0 jumpers to 1, 1 \nthen hit enter") # Get the host from the command line argument. Can be numeric or hostname. HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1' print '\nStarting client' client = MemClient(host=HOST) # Read FPGA type and revision rev_id = client.reg_read(REV_ID_BASE) type_id = rev_id & 0x0000FFFF rev = (rev_id >> 16) & 0x0000FFFF print 'FPGA load type ID: %04X' % type_id print 'FPGA load revision: %04X' % rev start_time = time.time() print("Setting up system parameters.\n") client.reg_write(SYSTEM_CLOCK_BASE, ((LUT_NCO_DIVIDER << 16) | SYSTEM_CLOCK_DIVIDER)) client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES)
N = 7 #Number of samples to average (LTC2380-24) vfs = 10.0 # Full-scale voltage, VREF * 2 for LTC25xx family nco_word_width = 32 # A property of the NCO in the FPGA design master_clock = 50000000 # Relies on proper configuration of LTC6954 divider bin_number = 50 # Number of cycles over the time record for sine signal sample_rate = master_clock / (SYSTEM_CLOCK_DIVIDER + 1 ) # 250ksps for 50M clock, 200 clocks per sample cycles_per_sample = float(bin_number) / float(NUM_SAMPLES) cycles_per_dac_sample = cycles_per_sample / (SYSTEM_CLOCK_DIVIDER + 1) tuning_word = int(cycles_per_dac_sample * 2**nco_word_width) print("Tuning Word:" + str(tuning_word)) print('Starting client') client = MemClient(host=HOST) #First thing's First!! Configure clocks... LTC6954_configure(client, 0x04) #Read FPGA type and revision type_rev_check(client, 0xABCD, 0x1246) print("Setting up system parameters.\n") client.reg_write(SYSTEM_CLOCK_BASE, SYSTEM_CLOCK_DIVIDER) client.reg_write(SYSTEM_CLOCK_BASE, (LUT_NCO_DIVIDER << 16 | SYSTEM_CLOCK_DIVIDER)) client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES) #datapath fields: lut_addr_select, dac_a_select, dac_b_select[1:0], fifo_data_select #lut addresses: 0=lut_addr_counter, 1=dac_a_data_signed, 2=0x4000, 3=0xC000 # DAC A: # .data0x ( nco_sin_out ),
PULSE_LOW = 20000 PULSE_HIGH = 100000 PULSE_VAL = 50000 nco_word_width = 32 master_clock = 50000000 bin_number = 23 # Number of cycles over the time record sample_rate = master_clock / (SYSTEM_CLOCK_DIVIDER + 1 ) # 250ksps for 50M clock, 200 clocks per sample cycles_per_sample = float(bin_number) / float(NUM_SAMPLES) cycles_per_dac_sample = cycles_per_sample / (SYSTEM_CLOCK_DIVIDER + 1) tuning_word = int(cycles_per_dac_sample * 2**nco_word_width) print("Tuning Word:" + str(tuning_word)) print('Starting client') client = MemClient(host=HOST) #First thing's First!! Configure clocks... LTC6954_configure(client) #Check FPGA type and revision type_rev_check(client, 0xABCD, 0x1246) print("Setting up system parameters.\n") client.reg_write(SYSTEM_CLOCK_BASE, SYSTEM_CLOCK_DIVIDER) client.reg_write(SYSTEM_CLOCK_BASE, (LUT_NCO_DIVIDER << 16 | SYSTEM_CLOCK_DIVIDER)) client.reg_write(NUM_SAMPLES_BASE, NUM_SAMPLES) pll_locked = client.reg_read(DATA_READY_BASE) # Check data ready signal if ((pll_locked & 0x02) == 0x02): print("PLL is LOCKED!") else:
# Get the host from the command line argument. Can be numeric or hostname. # If no host given, assume local machine (such as the SoCkit board itself) HOST = sys.argv[1] if len(sys.argv) == 2 else '127.0.0.1' # For example, if you're using the default fixed address that the SoCkit assigns # itself if DHCP fails, you would run: # python DC2390_hello_world.py "192.168.1.231" # If you're running this script ON the sockit board itself, you would run: # python DC2390_hello_world.py # Now we create an instance of MemClient, called "client", pointing it at # the SoCkit's IP address. This is the "pipeline" that allows us to communicate. print('Starting client') client = MemClient(host=HOST) # First thing's First!! Unfortunately we can't even blink a light without first # Configuring the clocks, which are provided from a crystal oscillator and # LTC6954 clock distribution divider / driver LTC6954_configure(client) # Look in DC2390_functions.py for details... # The following routines read and write registers in the FPGA. These can be # either read or write (or both), depending on the exact design. # But fundamentally, when reading or writing a register from a script such as # this one, you are reading or setting the state of a signal in the FPGA design. # The addresses of the registers we will be talking to are defined in # DC2390_functions.py, imported above. If you open it up, you will see these lines: # # REV_ID_BASE = 0x10