def __init__(self):
Pyro.core.ObjBase.__init__(self)
self._connected = False
self.addr = None
self.source = {}
corelog.info("Connecting to GavrtDB")
self.gdb = GavrtDB(rw=True)
rec = self.gdb.get("SELECT * FROM antenna_cmd ORDER BY ID DESC LIMIT 1")
if rec:
self.source = dict(name=rec['Name'][0],RA=rec['RA'][0],Dec=rec['Dec'][0],id=int(rec['SourceID'][0]))
corelog.info("Got most recent source: %s" % (rec['Name'][0]))
else:
corelog.error("Could not find a most recent sournce in the antenna_cmd table.")
def setPLL(self, d):
if d is None:
return
corelog.debug("Setting prescaler = 8/9")
self.WriteReg(0x16, 0x04)
corelog.debug("Setting r = 100 (100MHz ref)")
self.WriteReg(0x11, 100)
corelog.debug("Setting a: %d" % d["a"])
self.WriteReg(0x13, d["a"])
(h, l) = divmod(d["b"], 256)
corelog.debug("Setting b: %d=%d*256+%d" % (d["b"], h, l))
self.WriteReg(0x14, l)
self.WriteReg(0x15, h)
VCOdivVal = d["VCOdiv"] - 2
if VCOdivVal < 0 or VCOdivVal > 4:
corelog.error("Got bad VCOdivider: %d Original valud %d. Proceeding using 2" % (VCOdivVal, d["VCOdiv"]))
VCOdivVal = 0
corelog.debug("Setting VCOdiv: %d, reg: %d" % (d["VCOdiv"], VCOdivVal))
self.WriteReg(0x1E0, VCOdivVal)
finaldiv = d["finaldiv"]
if finaldiv == 1:
corelog.debug("Bypassing final divider")
self.WriteReg(0x197, 0x80)
self.WriteReg(0x191, 0x80)
else:
cycles = finaldiv / 2 - 1
corelog.debug("cycles= %d cyclereg: 0x%02x" % (cycles, cycles * 16 + cycles))
self.WriteReg(0x197, 0x00)
self.WriteReg(0x191, 0x00)
self.WriteReg(0x196, cycles * 16 + cycles)
self.WriteReg(0x190, cycles * 16 + cycles)
self.WriteReg(0x232, 1)
corelog.debug("Calibrating VCO")
self.WriteReg(0x18, 0x06)
self.WriteReg(0x232, 1)
self.WriteReg(0x18, 0x07)
self.WriteReg(0x232, 1)
def connect(self):
"""
Open a TCP connection to the RCT
"""
self.sock = socket.socket(socket.AF_INET,socket.SOCK_STREAM)
self.sock.setsockopt(socket.SOL_SOCKET, socket.SO_REUSEADDR, 1)
self.sock.bind(('',9002))
for addr in RCT_ADDRS:
tries = 0
while tries < 1:
try:
self.sock.connect(addr)
corelog.info("RCT Connected at %s" % (str(addr)))
break
except Exception, e:
corelog.info("Could not connect to RCT on %s" % (str(addr)))
tries += 1
if tries <1:
self.sock.setblocking(False)
self._connected = True
return
else:
corelog.error("Could not connect to RCT on %s" % (str(addr)))
self._connected = False
def calcPLL(self, f):
"""
Calculate the PLL parameters
"""
if f > 1125:
corelog.error("Attempting to set frequency higher than 1125 MHz. Value was: %f MHz" % f)
return None
finaldiv = 1
while f * finaldiv < 291:
finaldiv *= 2
if finaldiv > 32:
corelog.error(
"IBOB ADC clock synthesizer cannot reach that frequency. would require a final divider of %d > 32"
% finaldiv
)
return None
forig = f
f = f * finaldiv
if f >= 875 and f <= 1125:
VCOdiv = 2
elif f >= 583 and f <= 750:
VCOdiv = 3
elif f >= 438 and f <= 562:
if finaldiv < 32:
f *= 2
finaldiv *= 2
VCOdiv = 2
else:
VCOdiv = 4
elif f >= 350 and f <= 450:
VCOdiv = 5
elif f >= 291 and f <= 375:
if finaldiv < 32:
finaldiv *= 2
f *= 2
VCOdiv = 3
else:
VCOdiv = 6
else:
corelog.error(
"IBOB ADC clock synthesizer cannot reach that frequency. forig: %f f: %f finaldiv: %d"
% (forig, f, finaldiv)
)
return None
(b, a) = divmod(f * VCOdiv, 8)
output = (b * 8 + a) / VCOdiv / finaldiv
corelog.info(
"Found PLL settings: forig: %f, f: %f, finaldiv: %d, VCOdiv: %d, b: %d, a: %d, VCO: %f expected output: %f",
(forig, f, finaldiv, VCOdiv, b, a, f * VCOdiv, output),
)
return dict(VCOdiv=VCOdiv, b=b, a=a, finaldiv=finaldiv, VCO=f, output=output)
