def main():
parser = argparse.ArgumentParser(
description="Generic ARM big.LITTLE configuration with "\
"example power models")
bL.addOptions(parser)
options = parser.parse_args()
if options.cpu_type != "timing":
m5.fatal("The power example script requires 'timing' CPUs.")
root = bL.build(options)
# Wire up some example power models to the CPUs
for cpu in root.system.descendants():
if not isinstance(cpu, m5.objects.BaseCPU):
continue
cpu.default_p_state = "ON"
cpu.power_model = CpuPowerModel()
bL.instantiate(options)
print "*" * 70
print "WARNING: The power numbers generated by this script are " \
"examples. They are not representative of any particular " \
"implementation or process."
print "*" * 70
# Dumping stats periodically
m5.stats.periodicStatDump(m5.ticks.fromSeconds(0.1E-3))
bL.run()
def require_file(path, fatal=False, mode=os.F_OK):
"""Test if a file exists and abort/skip test if not.
Arguments:
path -- File to test for.
Keyword arguments:
fatal -- Set to True to indicate that the test should fail
instead of being skipped.
modes -- Mode to test for, default to existence. See the
Python documentation for os.access().
"""
if os.access(path, mode):
return
else:
msg = "Test requires '%s'" % path
if not os.path.exists(path):
msg += " which does not exist."
else:
msg += " which has incorrect permissions."
if fatal:
m5.fatal(msg)
else:
skip_test(msg)
def add_option(*args, **kwargs):
"""Call "add_option" to the global options parser
"""
if (parser.has_option(args[0]) or
(len(args) > 1 and parser.has_option(args[1])) ):
m5.fatal("Duplicate option: %s" % str(args))
if called_parse_args:
m5.fatal("Can't add an option after calling SimpleOpts.parse_args")
parser.add_option(*args, **kwargs)
def setup(self, machine):
if self.mcpat: return
self.createMcPatConfig(machine)
self.debug('starting mcpat process')
try:
self.mcpat = subprocess.Popen(['mcpat', '-infile', self.mcpatConfig, '-print_level', '5'],
stdin=subprocess.PIPE,
stdout=subprocess.PIPE)
except OSError as e:
m5.fatal("Running mcpat failed (error {0.errno}): {0.strerror}".format(e))
self.mcpatOutputGrabber = McPatOutputGrabber(self.mcpat.stdout, hasMachineBuses(machine))
def require_sim_object(name, fatal=False):
"""Test if a SimObject exists and abort/skip test if not.
Arguments:
name -- Name of SimObject (string)
Keyword arguments:
fatal -- Set to True to indicate that the test should fail
instead of being skipped.
"""
if has_sim_object(name):
return
else:
msg = "Test requires the '%s' SimObject." % name
if fatal:
m5.fatal(msg)
else:
skip_test(msg)
def config_etrace(cpu_cls, cpu_list, options):
if issubclass(cpu_cls, m5.objects.DerivO3CPU):
# Assign the same file name to all cpus for now. This must be
# revisited when creating elastic traces for multi processor systems.
for cpu in cpu_list:
# Attach the elastic trace probe listener. Set the protobuf trace
# file names. Set the dependency window size equal to the cpu it
# is attached to.
cpu.traceListener = m5.objects.ElasticTrace(
instFetchTraceFile = options.inst_trace_file,
dataDepTraceFile = options.data_trace_file,
depWindowSize = 3 * cpu.numROBEntries)
# Make the number of entries in the ROB, LQ and SQ very
# large so that there are no stalls due to resource
# limitation as such stalls will get captured in the trace
# as compute delay. For replay, ROB, LQ and SQ sizes are
# modelled in the Trace CPU.
cpu.numROBEntries = 512;
cpu.LQEntries = 128;
cpu.SQEntries = 128;
else:
fatal("%s does not support data dependency tracing. Use a CPU model of"
" type or inherited from DerivO3CPU.", cpu_cls)
# Finalize the arguments and grab the opts so we can pass it on to our objects
(opts, args) = SimpleOpts.parse_args()
# get ISA for the default binary to run. This is mostly for simple testing
isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
# Default to running 'hello', use the compiled ISA to find the binary
binary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello'
# Check if there was a binary passed in via the command line and error if
# there are too many arguments
if len(args) == 1:
binary = args[0]
elif len(args) > 1:
SimpleOpts.print_help()
m5.fatal("Expected a binary to execute as positional argument")
# create the system we are going to simulate
system = System()
# Set the clock fequency of the system (and all of its children)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()
# Set up the system
system.mem_mode = 'timing' # Use timing accesses
system.mem_ranges = [AddrRange('512MB')] # Create an address range
# Create a simple CPU
system.cpu = TimingSimpleCPU()
parser = argparse.ArgumentParser(description='Simple memory tester')
parser.add_argument('--bandwidth', default=None)
parser.add_argument('--latency', default=None)
parser.add_argument('--latency_var', default=None)
args = parser.parse_args()
# even if this is only a traffic generator, call it cpu to make sure
# the scripts are happy
try:
cpu = TrafficGen(
config_file=os.path.join(os.path.dirname(os.path.abspath(__file__)),
"tgen-simple-mem.cfg"))
except NameError:
m5.fatal("protobuf required for simple memory test")
class MyMem(SimpleMemory):
if args.bandwidth:
bandwidth = args.bandwidth
if args.latency:
latency = args.latency
if args.latency_var:
latency_var = args.latency_var
# system simulated
system = System(cpu = cpu, physmem = MyMem(),
membus = IOXBar(width = 16),
clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain =
VoltageDomain()))
# Finalize the arguments and grab the opts so we can pass it on to our objects
(opts, args) = SimpleOpts.parse_args()
# get ISA for the default binary to run. This is mostly for simple testing
isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
# Default to running 'hello', use the compiled ISA to find the binary
#binary = 'tests/test-progs/polybench-c-4.2/2mm_ref'
binary = 'tests/parallel/polybench-c-4.2/heat-3d-fpga'
# Check if there was a binary passed in via the command line and error if
# there are too many arguments
if len(args) == 1:
binary = args[0]
elif len(args) > 1:
SimpleOpts.print_help()
m5.fatal("Expected a binary to execute as positional argument")
# create the system we are going to simulate
system = System()
# Set the clock fequency of the system (and all of its children)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '2GHz'
system.clk_domain.voltage_domain = VoltageDomain()
# Set up the system
system.mem_mode = 'timing' # Use timing accesses
system.mem_ranges = [AddrRange('512MB')] # Create an address range
#system.piobus = IOXBar()
# Create a simple CPU
# sleeping for sometime makes sure
# that the benchmark's output has been
# printed to the console
bench_file.write('sleep 5 \n')
bench_file.write('m5 exit \n')
bench_file.close()
return file_name
if __name__ == "__m5_main__":
(opts, args) = SimpleOpts.parse_args()
kernel, disk, cpu, benchmark, size, num_cpus = args
if not cpu in ['kvm', 'simple']:
m5.fatal("cpu not supported")
# create the system we are going to simulate
system = MySystem(kernel, disk, cpu, int(num_cpus))
# Exit from guest on workbegin/workend
system.exit_on_work_items = True
# Create and pass a script to the simulated system to run the reuired
# benchmark
system.readfile = writeBenchScript(m5.options.outdir, benchmark, size)
# set up the root SimObject and start the simulation
root = Root(full_system=True, system=system)
if system.getHostParallel():
isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
# Default to running 'hello', use the compiled ISA to find the binary
# grab the specific path to the binary
thispath = os.path.dirname(os.path.realpath(__file__))
binary = os.path.join(thispath, '../../', 'gem5/tests/test-progs/hello/bin/',
isa, 'linux/hello')
# Check if there was a binary passed in via the command line and error if
# there are too many arguments
if len(args) == 2:
binary = args[0]
tre_en = int(args[1])
elif len(args) > 2:
SimpleOpts.print_help()
m5.fatal(
"Expected binary_name and trace_replay_mode as positional arguments")
# create the system we are going to simulate
system = System()
# Set the clock fequency of the system (and all of its children)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = str(CLOCK_SPEED_GHZ) + 'GHz'
system.clk_domain.voltage_domain = VoltageDomain()
# Set up the system
system.mem_mode = 'timing' # Use timing accesses
mem_ranges = [AddrRange(0, size=0xE0100000)]
# system.mem_ranges = [AddrRange('8GB')] # Create an address range
system.mem_ranges = mem_ranges
import argparse
parser = argparse.ArgumentParser(description='Simple memory tester')
parser.add_argument('--bandwidth', default=None)
parser.add_argument('--latency', default=None)
parser.add_argument('--latency_var', default=None)
args = parser.parse_args()
# even if this is only a traffic generator, call it cpu to make sure
# the scripts are happy
try:
cpu = TrafficGen(config_file=os.path.join(
os.path.dirname(os.path.abspath(__file__)), "tgen-simple-mem.cfg"))
except NameError:
m5.fatal("protobuf required for simple memory test")
class MyMem(SimpleMemory):
if args.bandwidth:
bandwidth = args.bandwidth
if args.latency:
latency = args.latency
if args.latency_var:
latency_var = args.latency_var
# system simulated
system = System(cpu=cpu,
physmem=MyMem(),
membus=IOXBar(width=16),
def create_system(options, full_system, system, dma_ports, bootmem,
ruby_system):
if buildEnv['PROTOCOL'] != 'CHI':
m5.panic("This script requires the CHI build")
if options.num_dirs < 1:
m5.fatal('--num-dirs must be at least 1')
if options.num_l3caches < 1:
m5.fatal('--num-l3caches must be at least 1')
# read specialized classes from config file if provided
if options.chi_config:
chi_defs = read_config_file(options.chi_config)
elif options.topology == 'CustomMesh':
m5.fatal('--noc-config must be provided if topology is CustomMesh')
else:
# Use the defaults from CHI_config
from . import CHI_config as chi_defs
# NoC params
params = chi_defs.NoC_Params
# Node types
CHI_RNF = chi_defs.CHI_RNF
CHI_HNF = chi_defs.CHI_HNF
CHI_SNF_MainMem = chi_defs.CHI_SNF_MainMem
CHI_SNF_BootMem = chi_defs.CHI_SNF_BootMem
CHI_RNI_DMA = chi_defs.CHI_RNI_DMA
CHI_RNI_IO = chi_defs.CHI_RNI_IO
# Declare caches and controller types used by the protocol
# Notice tag and data accesses are not concurrent, so the a cache hit
# latency = tag + data + response latencies.
# Default response latencies are 1 cy for all controllers.
# For L1 controllers the mandatoryQueue enqueue latency is always 1 cy and
# this is deducted from the initial tag read latency for sequencer requests
# dataAccessLatency may be set to 0 if one wants to consider parallel
# data and tag lookups
class L1ICache(RubyCache):
dataAccessLatency = 1
tagAccessLatency = 1
size = options.l1i_size
assoc = options.l1i_assoc
class L1DCache(RubyCache):
dataAccessLatency = 2
tagAccessLatency = 1
size = options.l1d_size
assoc = options.l1d_assoc
class L2Cache(RubyCache):
dataAccessLatency = 6
tagAccessLatency = 2
size = options.l2_size
assoc = options.l2_assoc
class HNFCache(RubyCache):
dataAccessLatency = 10
tagAccessLatency = 2
size = options.l3_size
assoc = options.l3_assoc
# other functions use system.cache_line_size assuming it has been set
assert (system.cache_line_size.value == options.cacheline_size)
cpu_sequencers = []
mem_cntrls = []
mem_dests = []
network_nodes = []
network_cntrls = []
hnf_dests = []
all_cntrls = []
# Creates on RNF per cpu with priv l2 caches
assert (len(system.cpu) == options.num_cpus)
ruby_system.rnf = [
CHI_RNF([cpu], ruby_system, L1ICache, L1DCache,
system.cache_line_size.value) for cpu in system.cpu
]
for rnf in ruby_system.rnf:
rnf.addPrivL2Cache(L2Cache)
cpu_sequencers.extend(rnf.getSequencers())
all_cntrls.extend(rnf.getAllControllers())
network_nodes.append(rnf)
network_cntrls.extend(rnf.getNetworkSideControllers())
# Look for other memories
other_memories = []
if bootmem:
other_memories.append(bootmem)
if getattr(system, 'sram', None):
other_memories.append(getattr(system, 'sram', None))
on_chip_mem_ports = getattr(system, '_on_chip_mem_ports', None)
if on_chip_mem_ports:
other_memories.extend([p.simobj for p in on_chip_mem_ports])
# Create the LLCs cntrls
sysranges = [] + system.mem_ranges
for m in other_memories:
sysranges.append(m.range)
CHI_HNF.createAddrRanges(sysranges, system.cache_line_size.value,
options.num_l3caches)
ruby_system.hnf = [
CHI_HNF(i, ruby_system, HNFCache, None)
for i in range(options.num_l3caches)
]
for hnf in ruby_system.hnf:
network_nodes.append(hnf)
network_cntrls.extend(hnf.getNetworkSideControllers())
assert (hnf.getAllControllers() == hnf.getNetworkSideControllers())
all_cntrls.extend(hnf.getAllControllers())
hnf_dests.extend(hnf.getAllControllers())
# Create the memory controllers
# Notice we don't define a Directory_Controller type so we don't use
# create_directories shared by other protocols.
ruby_system.snf = [
CHI_SNF_MainMem(ruby_system, None, None)
for i in range(options.num_dirs)
]
for snf in ruby_system.snf:
network_nodes.append(snf)
network_cntrls.extend(snf.getNetworkSideControllers())
assert (snf.getAllControllers() == snf.getNetworkSideControllers())
mem_cntrls.extend(snf.getAllControllers())
all_cntrls.extend(snf.getAllControllers())
mem_dests.extend(snf.getAllControllers())
if len(other_memories) > 0:
ruby_system.rom_snf = [
CHI_SNF_BootMem(ruby_system, None, m) for m in other_memories
]
for snf in ruby_system.rom_snf:
network_nodes.append(snf)
network_cntrls.extend(snf.getNetworkSideControllers())
all_cntrls.extend(snf.getAllControllers())
mem_dests.extend(snf.getAllControllers())
# Creates the controller for dma ports and io
if len(dma_ports) > 0:
ruby_system.dma_rni = [
CHI_RNI_DMA(ruby_system, dma_port, None) for dma_port in dma_ports
]
for rni in ruby_system.dma_rni:
network_nodes.append(rni)
network_cntrls.extend(rni.getNetworkSideControllers())
all_cntrls.extend(rni.getAllControllers())
if full_system:
ruby_system.io_rni = CHI_RNI_IO(ruby_system, None)
network_nodes.append(ruby_system.io_rni)
network_cntrls.extend(ruby_system.io_rni.getNetworkSideControllers())
all_cntrls.extend(ruby_system.io_rni.getAllControllers())
# Assign downstream destinations
for rnf in ruby_system.rnf:
rnf.setDownstream(hnf_dests)
if len(dma_ports) > 0:
for rni in ruby_system.dma_rni:
rni.setDownstream(hnf_dests)
if full_system:
ruby_system.io_rni.setDownstream(hnf_dests)
for hnf in ruby_system.hnf:
hnf.setDownstream(mem_dests)
# Setup data message size for all controllers
for cntrl in all_cntrls:
cntrl.data_channel_size = params.data_width
# Network configurations
# virtual networks: 0=request, 1=snoop, 2=response, 3=data
ruby_system.network.number_of_virtual_networks = 4
ruby_system.network.control_msg_size = params.cntrl_msg_size
ruby_system.network.data_msg_size = params.data_width
ruby_system.network.buffer_size = params.router_buffer_size
# Incorporate the params into options so it's propagated to
# makeTopology and create_topology the parent scripts
for k in dir(params):
if not k.startswith('__'):
setattr(options, k, getattr(params, k))
if options.topology == 'CustomMesh':
topology = create_topology(network_nodes, options)
elif options.topology in ['Crossbar', 'Pt2Pt']:
topology = create_topology(network_cntrls, options)
else:
m5.fatal("%s not supported!" % options.topology)
return (cpu_sequencers, mem_cntrls, topology)
def config_scheme(cpu_cls, cpu_list, options):
if issubclass(cpu_cls, m5.objects.DerivO3CPU):
# Assign the same file name to all cpus for now.
if options.scheme == None or options.mem_model == None:
fatal(
"Need to provide scheme and mem_model to run simulation with DerivO3CPU"
)
if options.scheme == "UnsafeBaseline":
print "**********"
print "info: Configure for DerivO3CPU. scheme=%s; mem_model=%s, mshr_size=%d"\
% (options.scheme, options.mem_model, options.MSHR_size)
print "**********"
else:
print "**********"
print "info: Configure for DerivO3CPU. scheme=%s; mem_model=%s, MSHR_size=%d"\
% (options.scheme, options.mem_model, options.MSHR_size)
print "STT=%d; impChannel=%d"\
% (options.STT, options.impChannel)
print "**********"
for cpu in cpu_list:
if len(options.scheme) != 0:
cpu.scheme = options.scheme
if len(options.mem_model) != 0:
cpu.mem_model = options.mem_model
if options.threat_model:
cpu.threat_model = options.threat_model
## Jiyong, STT: STT related configurations passed to gem5 O3CPU
if options.STT:
cpu.STT = True
else:
cpu.STT = False
if options.impChannel:
cpu.impChannel = True
else:
cpu.impChannel = False
if options.moreTransTypes:
cpu.moreTransTypes = options.moreTransTypes
else:
cpu.moreTransTypes = 0
if options.ifPrintROB:
cpu.ifPrintROB = True
else:
cpu.ifPrintROB = False
## Jiyong, STT: STT-profiling related configurations passed to genHitHistogramem5 O3CPU
if options.enable_STT_overhead_profiling:
cpu.enable_STT_overhead_profiling = True
else:
cpu.enable_STT_overhead_profiling = False
if options.enable_loadhit_trace_profiling:
cpu.enable_loadhit_trace_profiling = True
else:
cpu.enable_loadhit_trace_profiling = False
if options.genHitTrace_NumLoads:
cpu.genHitTrace_NumLoads = options.genHitTrace_NumLoads
else:
cpu.genHitTrace_NumLoads = 0
if options.genHitTrace_WkldName:
cpu.genHitTrace_WkldName = options.genHitTrace_WkldName
## Jiyong, SDO configs
if options.scheme == "SDO":
cpu.enable_MLDOM = True
print "### SDO is enabled"
else:
cpu.enable_MLDOM = False
print "### SDO is disabled"
if options.pred_type:
assert (cpu.enable_MLDOM)
cpu.pred_type = options.pred_type
print "### SDO predictor is: %s" % options.pred_type
else:
assert not cpu.enable_MLDOM
cpu.pred_type = "none"
if options.pred_option:
assert (cpu.enable_MLDOM)
cpu.pred_option = options.pred_option
print "### SDO predictor has option: %d" % options.pred_option
if options.subpred1_type:
assert (cpu.enable_MLDOM)
cpu.tournament_pred1_type = options.subpred1_type
else:
cpu.tournament_pred1_type = "none"
if options.subpred2_type:
assert (cpu.enable_MLDOM)
cpu.tournament_pred2_type = options.subpred2_type
else:
cpu.tournament_pred2_type = "none"
if options.subpred3_type:
assert (cpu.enable_MLDOM)
cpu.tournament_pred3_type = options.subpred3_type
else:
cpu.tournament_pred3_type = "none"
cpu.expose_only = options.expose_only
cpu.disable_2ndld = options.disable_2ndld
cpu.TLB_defense = options.TLB_defense
cpu.enable_OblS_contention = options.enable_OblS_contention
else:
print "not DerivO3CPU"