def DefineLinebuffer(cirb: CoreIRBackend,
inType: ArrayKind,
outType: ArrayKind,
imgType: ArrayKind,
has_valid=False):
"""
Implements a linebuffer for image pipelines. inType is an array of how many pixels
are inputted per clock. outType is an array of how many pixels are emitted per clock.
imgType is the size of the total image.
inType and outType are nested arrays of elementType if doing linebuffer over a 2d (or higher dimension)
image. Their nesting should match number of dimensions.
inType, outType, and imgType must be arrays of elementType
Args:
cirb: The CoreIR backend currently be used
inType: The type of the input every clock
outType: The type of the output every clock following warmup
imgType: The type of the complete image
elementType: The elements of the image, typically this is a pixel
has_valid: Whether this module should have an output port denoting if output data
is valid this clock
Returns:
A module with the following ports:
I : In(inType)
out : Out(outType)
wen : In(Bit) -- this is a clock enable port. TODO: wrap this module and call it CE
AND IF VALID SET
valid : Out(Bit)
valid_chain : Out(Bit) (this is an internal property that is being
exposed on linebuffer's external interface. always send it to a term)
"""
# Reason for weird False/True settings in get_type
# get_type does some funky things, False means not input, and since
# looking from inside module, output port is an input as it receives input
# But, linebuffer wants these ports from perspective of outside,
# so need inverse, inputs are BitIns and outputs are Bits
cirInType = cirb.get_type(inType, False)
cirOutType = cirb.get_type(outType, True)
cirImgType = cirb.get_type(imgType, False)
strForValid = "_Valid" if has_valid else ""
name = "linebuffer_in{}_out{}_img{}{}".format(cleanName(str(inType)),
cleanName(str(outType)),
cleanName(str(imgType)),
strForValid)
# this is the linebuffer with the outputs as a flat array, unsplit
defToReturn = DefineCircuitFromGeneratorWrapper(
cirb, "commonlib", "linebuffer", "unioned_" + name,
["mantle", "coreir", "global"], {
"input_type": cirInType,
"output_type": cirOutType,
"image_type": cirImgType,
"has_valid": has_valid
})
return defToReturn
def DefineDehydrate(cirb: CoreIRBackend, T: Kind):
"""
Convert a nested type to a flat array of bits
Aetherling Type: {1, T} -> {1, Bit[width(T)]}
This returns a circuit definition.
Args:
cirb: The CoreIR backend currently be used
T: The type to dehydrate
Returns:
A module with the following ports:
I : In(T)
out : Out(Array(width(T), Bit))
The module also has the following data:
size: width(T)
"""
cirType = cirb.get_type(T, True)
name = "dehydrate_t{}".format(cleanName(str(T)))
defToReturn = DefineCircuitFromGeneratorWrapper(
cirb, "aetherlinglib", "dehydrate", name,
["commonlib", "mantle", "coreir", "global"], {"hydratedType": cirType})
defToReturn.size = cirType.size
return defToReturn
def Flatten(cirb: CoreIRBackend, inputType: Kind, singleElementOutputType: Kind) -> Circuit:
"""
Flatten a nested list to a single list. The nested list can be flattened across multiple dimensions
with a single flatten node. The output list can be nested, but if so must be flatter than the input list.
Aetherling Type: T[k]...[s] -> T[k*...*s] (... means potentially many lists/lengths)
:param cirb: The CoreIR backend currently be used
:param inputType: The nested lists input type
:param singleElementOutputType: The element type T that will be emitted. It can be a list itself, but it must be
an element (at some level of nesting) in inputType.
:return: A list with elements of type singleElementOutputType that is of the appropriate length
for the flatteneing.
I : In(inputType)
O : Out(Array(singleElementOutputType, k*...*s))
"""
cirInputType = cirb.get_type(inputType, True)
cirSingleEleementOutputType = cirb.get_type(singleElementOutputType, True)
name = "dehydrate_tin{}_tout".format(cleanName(str(cirInputType)), cleanName(str(singleElementOutputType)))
moduleToReturn = CircuitInstanceFromGeneratorWrapper(cirb, "aetherlinglib", "flatten", name,
["commonlib", "mantle", "coreir", "global"],
{"inputType": cirInputType,
"singleElementOutputType": cirSingleEleementOutputType})
return moduleToReturn
