def implement_test_case(self, io_map, input_values, output_signals, output_values, time_step):
""" Implement the test case check and assertion whose I/Os values
are described in input_values and output_values dict """
test_statement = Statement()
input_msg = ""
# Adding input setting
for input_tag in input_values:
input_signal = io_map[input_tag]
# FIXME: correct value generation depending on signal precision
input_value = input_values[input_tag]
test_statement.add(get_input_assign(input_signal, input_value))
input_msg += get_input_msg(input_tag, input_signal, input_value)
test_statement.add(Wait(time_step * (self.stage_num + 2)))
# Adding output value comparison
for output_tag in output_signals:
output_signal = output_signals[output_tag]
output_value = output_values[output_tag]
output_cst_value = Constant(output_value, precision=output_signal.get_precision())
value_msg = get_output_value_msg(output_signal, output_value)
test_pass_cond, check_statement = get_output_check_statement(output_signal, output_tag, output_cst_value)
test_statement.add(check_statement)
assert_statement = Assert(
test_pass_cond,
"\"unexpected value for inputs {input_msg}, output {output_tag}, expecting {value_msg}, got: \"".format(input_msg = input_msg, output_tag = output_tag, value_msg = value_msg),
severity = Assert.Failure
)
test_statement.add(assert_statement)
return test_statement
def generate_embedded_testbench(self, tc_list, io_map, input_signals, output_signals, time_step, test_fname="test.input"):
""" Generate testbench with embedded input and output data """
self_component = self.implementation.get_component_object()
self_instance = self_component(io_map = io_map, tag = "tested_entity")
test_statement = Statement()
for index, (input_values, output_values) in enumerate(tc_list):
test_statement.add(
self.implement_test_case(io_map, input_values, output_signals, output_values, time_step, index=index)
)
reset_statement = self.get_reset_statement(io_map, time_step)
testbench = CodeEntity("testbench")
test_process = Process(
reset_statement,
test_statement,
# end of test
Assert(
Constant(0, precision = ML_Bool),
" \"end of test, no error encountered \"",
severity = Assert.Warning
),
# infinite end loop
WhileLoop(
Constant(1, precision=ML_Bool),
Statement(
Wait(time_step * (self.stage_num + 2)),
)
)
)
testbench_scheme = Statement(
self_instance,
test_process
)
if self.pipelined:
half_time_step = time_step / 2
assert (half_time_step * 2) == time_step
# adding clock process for pipelined bench
clk_process = Process(
Statement(
ReferenceAssign(
io_map["clk"],
Constant(1, precision = ML_StdLogic)
),
Wait(half_time_step),
ReferenceAssign(
io_map["clk"],
Constant(0, precision = ML_StdLogic)
),
Wait(half_time_step),
)
)
testbench_scheme.push(clk_process)
testbench.add_process(testbench_scheme)
return [testbench]
def generate_auto_test(self,
test_num=10,
test_range=Interval(-1.0, 1.0),
debug=False,
time_step=10):
""" time_step: duration of a stage (in ns) """
# instanciating tested component
# map of input_tag -> input_signal and output_tag -> output_signal
io_map = {}
# map of input_tag -> input_signal, excludind commodity signals
# (e.g. clock and reset)
input_signals = {}
# map of output_tag -> output_signal
output_signals = {}
# excluding clock and reset signals from argument list
# reduced_arg_list = [input_port for input_port in self.implementation.get_arg_list() if not input_port.get_tag() in ["clk", "reset"]]
reduced_arg_list = self.implementation.get_arg_list()
for input_port in reduced_arg_list:
input_tag = input_port.get_tag()
input_signal = Signal(input_tag + "_i",
precision=input_port.get_precision(),
var_type=Signal.Local)
io_map[input_tag] = input_signal
if not input_tag in ["clk", "reset"]:
input_signals[input_tag] = input_signal
for output_port in self.implementation.get_output_port():
output_tag = output_port.get_tag()
output_signal = Signal(output_tag + "_o",
precision=output_port.get_precision(),
var_type=Signal.Local)
io_map[output_tag] = output_signal
output_signals[output_tag] = output_signal
# building list of test cases
tc_list = []
self_component = self.implementation.get_component_object()
self_instance = self_component(io_map=io_map, tag="tested_entity")
test_statement = Statement()
# initializing random test case generator
self.init_test_generator()
# Appending standard test cases if required
if self.auto_test_std:
tc_list += self.standard_test_cases
for i in range(test_num):
input_values = self.generate_test_case(input_signals, io_map, i,
test_range)
tc_list.append((input_values, None))
def compute_results(tc):
""" update test case with output values if required """
input_values, output_values = tc
if output_values is None:
return input_values, self.numeric_emulate(input_values)
else:
return tc
# filling output values
tc_list = [compute_results(tc) for tc in tc_list]
for input_values, output_values in tc_list:
test_statement.add(
self.implement_test_case(io_map, input_values, output_signals,
output_values, time_step))
testbench = CodeEntity("testbench")
test_process = Process(
test_statement,
# end of test
Assert(Constant(0, precision=ML_Bool),
" \"end of test, no error encountered \"",
severity=Assert.Failure))
testbench_scheme = Statement(self_instance, test_process)
if self.pipelined:
half_time_step = time_step / 2
assert (half_time_step * 2) == time_step
# adding clock process for pipelined bench
clk_process = Process(
Statement(
ReferenceAssign(io_map["clk"],
Constant(1, precision=ML_StdLogic)),
Wait(half_time_step),
ReferenceAssign(io_map["clk"],
Constant(0, precision=ML_StdLogic)),
Wait(half_time_step),
))
testbench_scheme.push(clk_process)
testbench.add_process(testbench_scheme)
return [testbench]
def generate_auto_test(self,
test_num=10,
test_range=Interval(-1.0, 1.0),
debug=False,
time_step=10):
""" time_step: duration of a stage (in ns) """
# instanciating tested component
# map of input_tag -> input_signal and output_tag -> output_signal
io_map = {}
# map of input_tag -> input_signal, excludind commodity signals
# (e.g. clock and reset)
input_signals = {}
# map of output_tag -> output_signal
output_signals = {}
# excluding clock and reset signals from argument list
# reduced_arg_list = [input_port for input_port in self.implementation.get_arg_list() if not input_port.get_tag() in ["clk", "reset"]]
reduced_arg_list = self.implementation.get_arg_list()
for input_port in reduced_arg_list:
input_tag = input_port.get_tag()
input_signal = Signal(input_tag + "_i",
precision=input_port.get_precision(),
var_type=Signal.Local)
io_map[input_tag] = input_signal
if not input_tag in ["clk", "reset"]:
input_signals[input_tag] = input_signal
for output_port in self.implementation.get_output_port():
output_tag = output_port.get_tag()
output_signal = Signal(output_tag + "_o",
precision=output_port.get_precision(),
var_type=Signal.Local)
io_map[output_tag] = output_signal
output_signals[output_tag] = output_signal
# building list of test cases
tc_list = []
self_component = self.implementation.get_component_object()
self_instance = self_component(io_map=io_map, tag="tested_entity")
test_statement = Statement()
# initializing random test case generator
self.init_test_generator()
# Appending standard test cases if required
if self.auto_test_std:
tc_list += self.standard_test_cases
for i in range(test_num):
input_values = self.generate_test_case(input_signals, io_map, i,
test_range)
tc_list.append((input_values, None))
def compute_results(tc):
""" update test case with output values if required """
input_values, output_values = tc
if output_values is None:
return input_values, self.numeric_emulate(input_values)
else:
return tc
# filling output values
tc_list = [compute_results(tc) for tc in tc_list]
for input_values, output_values in tc_list:
input_msg = ""
# Adding input setting
for input_tag in input_values:
input_signal = io_map[input_tag]
# FIXME: correct value generation depending on signal precision
input_value = input_values[input_tag]
test_statement.add(
ReferenceAssign(
input_signal,
Constant(input_value,
precision=input_signal.get_precision())))
value_msg = input_signal.get_precision().get_cst(
input_value, language=VHDL_Code).replace('"', "'")
value_msg += " / " + hex(input_signal.get_precision(
).get_base_format().get_integer_coding(input_value))
input_msg += " {}={} ".format(input_tag, value_msg)
test_statement.add(Wait(time_step * self.stage_num))
# Adding output value comparison
for output_tag in output_signals:
output_signal = output_signals[output_tag]
output_value = Constant(
output_values[output_tag],
precision=output_signal.get_precision())
output_precision = output_signal.get_precision()
expected_dec = output_precision.get_cst(
output_values[output_tag],
language=VHDL_Code).replace('"', "'")
expected_hex = " / " + hex(
output_precision.get_base_format().get_integer_coding(
output_values[output_tag]))
value_msg = "{} / {}".format(expected_dec, expected_hex)
test_pass_cond = Comparison(output_signal,
output_value,
specifier=Comparison.Equal,
precision=ML_Bool)
test_statement.add(
ConditionBlock(
LogicalNot(test_pass_cond, precision=ML_Bool),
Report(
Concatenation(
" result for {}: ".format(output_tag),
Conversion(TypeCast(
output_signal,
precision=ML_StdLogicVectorFormat(
output_signal.get_precision(
).get_bit_size())),
precision=ML_String),
precision=ML_String))))
test_statement.add(
Assert(
test_pass_cond,
"\"unexpected value for inputs {input_msg}, output {output_tag}, expecting {value_msg}, got: \""
.format(input_msg=input_msg,
output_tag=output_tag,
value_msg=value_msg),
severity=Assert.Failure))
testbench = CodeEntity("testbench")
test_process = Process(
test_statement,
# end of test
Assert(Constant(0, precision=ML_Bool),
" \"end of test, no error encountered \"",
severity=Assert.Failure))
testbench_scheme = Statement(self_instance, test_process)
if self.pipelined:
half_time_step = time_step / 2
assert (half_time_step * 2) == time_step
# adding clock process for pipelined bench
clk_process = Process(
Statement(
ReferenceAssign(io_map["clk"],
Constant(1, precision=ML_StdLogic)),
Wait(half_time_step),
ReferenceAssign(io_map["clk"],
Constant(0, precision=ML_StdLogic)),
Wait(half_time_step),
))
testbench_scheme.push(clk_process)
testbench.add_process(testbench_scheme)
return [testbench]
def generate_datafile_testbench(self, tc_list, io_map, input_signals, output_signals, time_step, test_fname="test.input"):
""" Generate testbench with input and output data externalized in
a data file """
# textio function to read hexadecimal text
def FCT_HexaRead_gen(input_format):
legalized_input_format = input_format
FCT_HexaRead = FunctionObject("hread", [HDL_LINE, legalized_input_format], ML_Void, FunctionOperator("hread", void_function=True, arity=2))
return FCT_HexaRead
# textio function to read binary text
FCT_Read = FunctionObject("read", [HDL_LINE, ML_StdLogic], ML_Void, FunctionOperator("read", void_function=True, arity=2))
input_line = Variable("input_line", precision=HDL_LINE, var_type=Variable.Local)
# building ordered list of input and output signal names
input_signal_list = [sname for sname in input_signals.keys()]
input_statement = Statement()
for input_name in input_signal_list:
input_format = input_signals[input_name].precision
input_var = Variable(
"v_" + input_name,
precision=input_format,
var_type=Variable.Local)
if input_format is ML_StdLogic:
input_statement.add(FCT_Read(input_line, input_var))
else:
input_statement.add(FCT_HexaRead_gen(input_format)(input_line, input_var))
input_statement.add(ReferenceAssign(input_signals[input_name], input_var))
output_signal_list = [sname for sname in output_signals.keys()]
output_statement = Statement()
for output_name in output_signal_list:
output_format = output_signals[output_name].precision
output_var = Variable(
"v_" + output_name,
precision=output_format,
var_type=Variable.Local)
if output_format is ML_StdLogic:
output_statement.add(FCT_Read(input_line, output_var))
else:
output_statement.add(FCT_HexaRead_gen(output_format)(input_line, output_var))
output_signal = output_signals[output_name]
#value_msg = get_output_value_msg(output_signal, output_value)
test_pass_cond, check_statement = get_output_check_statement(output_signal, output_name, output_var)
input_msg = multi_Concatenation(*tuple(sum([[" %s=" % input_tag, signal_str_conversion(input_signals[input_tag], input_signals[input_tag].precision)] for input_tag in input_signal_list], [])))
output_statement.add(check_statement)
assert_statement = Assert(
test_pass_cond,
multi_Concatenation(
"unexpected value for inputs ",
input_msg,
" expecting :",
signal_str_conversion(output_var, output_format),
" got :",
signal_str_conversion(output_signal, output_format),
precision = ML_String
),
severity=Assert.Failure
)
output_statement.add(assert_statement)
self_component = self.implementation.get_component_object()
self_instance = self_component(io_map = io_map, tag = "tested_entity")
test_statement = Statement()
DATA_FILE_NAME = test_fname
with open(DATA_FILE_NAME, "w") as data_file:
# dumping column tags
data_file.write("# " + " ".join(input_signal_list + output_signal_list) + "\n")
def get_raw_cst_string(cst_format, cst_value):
size = int((cst_format.get_bit_size() + 3) / 4)
return ("{:x}").format(cst_format.get_base_format().get_integer_coding(cst_value)).zfill(size)
for input_values, output_values in tc_list:
# TODO; generate test data file
cst_list = []
for input_name in input_signal_list:
input_value = input_values[input_name]
input_format = input_signals[input_name].get_precision()
cst_list.append(get_raw_cst_string(input_format, input_value))
for output_name in output_signal_list:
output_value = output_values[output_name]
output_format = output_signals[output_name].get_precision()
cst_list.append(get_raw_cst_string(output_format, output_value))
# dumping line into file
data_file.write(" ".join(cst_list) + "\n")
input_stream = Variable("data_file", precision=HDL_FILE, var_type=Variable.Local)
file_status = Variable("file_status", precision=HDL_OPEN_FILE_STATUS, var_type=Variable.Local)
FCT_EndFile = FunctionObject("endfile", [HDL_FILE], ML_Bool, FunctionOperator("endfile", arity=1))
FCT_OpenFile = FunctionObject(
"FILE_OPEN", [HDL_OPEN_FILE_STATUS, HDL_FILE, ML_String], ML_Void,
FunctionOperator(
"FILE_OPEN",
arg_map={0: FO_Arg(0), 1: FO_Arg(1), 2: FO_Arg(2), 3: "READ_MODE"},
void_function=True))
FCT_ReadLine = FunctionObject(
"readline", [HDL_FILE, HDL_LINE], ML_Void,
FunctionOperator("readline", void_function=True, arity=2))
reset_statement = self.get_reset_statement(io_map, time_step)
OPEN_OK = Constant("OPEN_OK", precision=HDL_OPEN_FILE_STATUS)
testbench = CodeEntity("testbench")
test_process = Process(
reset_statement,
FCT_OpenFile(file_status, input_stream, DATA_FILE_NAME),
ConditionBlock(
Comparison(file_status, OPEN_OK, specifier=Comparison.NotEqual),
Assert(
Constant(0, precision=ML_Bool),
" \"failed to open file {}\"".format(DATA_FILE_NAME),
severity=Assert.Failure
)
),
# consume legend line
FCT_ReadLine(input_stream, input_line),
WhileLoop(
LogicalNot(FCT_EndFile(input_stream)),
Statement(
FCT_ReadLine(input_stream, input_line),
input_statement,
Wait(time_step * (self.stage_num + 2)),
output_statement,
),
),
# end of test
Assert(
Constant(0, precision = ML_Bool),
" \"end of test, no error encountered \"",
severity = Assert.Warning
),
# infinite end loop
WhileLoop(
Constant(1, precision=ML_Bool),
Statement(
Wait(time_step * (self.stage_num + 2)),
)
)
)
testbench_scheme = Statement(
self_instance,
test_process
)
if self.pipelined:
half_time_step = time_step / 2
assert (half_time_step * 2) == time_step
# adding clock process for pipelined bench
clk_process = Process(
Statement(
ReferenceAssign(
io_map["clk"],
Constant(1, precision = ML_StdLogic)
),
Wait(half_time_step),
ReferenceAssign(
io_map["clk"],
Constant(0, precision = ML_StdLogic)
),
Wait(half_time_step),
)
)
testbench_scheme.push(clk_process)
testbench.add_process(testbench_scheme)
return [testbench]