def __init__(self, sdrphy, dfi, sdram_geom, sdram_timing, pads, sdram_clk):
self.clk_freq = 80000000
phy_settings = sdrphy.settings
rdphase = phy_settings.rdphase
self.submodules.slave = Minicon(phy_settings, sdram_geom, sdram_timing)
self.submodules.tap = wishbone.Tap(self.slave.bus)
self.submodules.dc = dc = wishbone.DownConverter(32, phy_settings.nphases*flen(dfi.phases[rdphase].rddata))
self.submodules.master = wishbone.Initiator(self.genxfers(), bus=dc.wishbone_i)
self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, self.slave.bus)
self.submodules.sdrphy = self.sdrphy = sdrphy
self.dfi = dfi
self.pads = pads
self.specials += Instance("mt48lc4m16a2",
io_Dq=pads.dq,
i_Addr=pads.a,
i_Ba=pads.ba,
i_Clk=ClockSignal(),
i_Cke=pads.cke,
i_Cs_n=pads.cs_n,
i_Ras_n=pads.ras_n,
i_Cas_n=pads.cas_n,
i_We_n=pads.we_n,
i_Dqm=pads.dm
)
def __init__(self):
pads = Signal(8)
self.submodules.gp = Gpio(pads)
self.comb += pads[4:].eq(pads[:4])
self.submodules.wb = Wishbone()
self.submodules.dut = Master([
(self.gp, 0x00000100, 0xffffff00),
# (self.dds, 0x00010000, 0xffff0000),
(self.wb, 0x20000000, 0xe0000000),
# (self.spi, 0x40000000, 0xe0000000),
# (self.i2c, 0x60000000, 0xe0000000),
])
self.submodules.csrbanks = csrgen.BankArray(
self, lambda name, mem: {"dut": 0}[name])
self.submodules.ini = csr.Initiator(_test_gen())
self.submodules.con = csr.Interconnect(self.ini.bus,
self.csrbanks.get_buses())
#self.submodules.wbini = wishbone.Initiator(_test_gen_wb())
#self.submodules.wbtap = wishbone.Tap(self.dut.bus)
#self.submodules.wbcon = wishbone.InterconnectPointToPoint(
# self.wbini.bus, self.dut.bus)
self.submodules.wbtg = wishbone.Target(wishbone.TargetModel())
self.submodules.wbtap = wishbone.Tap(self.wbtg.bus)
self.submodules.wbic = wishbone.InterconnectPointToPoint(
self.wb.bus, self.wbtg.bus)
def __init__(self):
self.submodules.master = wishbone.Initiator(self.gen_reads())
self.pads = Record([("cs_n", 1), ("clk", 1), ("dq", 4)])
self.submodules.slave = SpiFlash(self.pads)
self.submodules.tap = wishbone.Tap(self.slave.bus)
self.submodules.intercon = wishbone.InterconnectPointToPoint(
self.master.bus, self.slave.bus)
self.cycle = 0
def __init__(self, ng):
g = DataFlowGraph()
d = Dumper(layout)
g.add_connection(ng, d)
self.submodules.slave = wishbone.Target(SlaveModel())
self.submodules.intercon = wishbone.InterconnectPointToPoint(
ng.wb, self.slave.bus)
self.submodules.ca = CompositeActor(g)
def __init__(self):
self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic],
self.ctler.nrowbits)
self.submodules.logger = DFILogger(self.ctler.dfi)
self.submodules.bridge = wishbone2lasmi.WB2LASMI(
l2_size // 4, self.xbar.get_master())
self.submodules.initiator = wishbone.Initiator(my_generator())
self.submodules.conn = wishbone.InterconnectPointToPoint(
self.initiator.bus, self.bridge.wishbone)
def __init__(self):
# The "wishbone.Initiator" library component runs our generator
# and manipulates the bus signals accordingly.
self.submodules.master = wishbone.Initiator(my_generator())
# The "wishbone.Target" library component examines the bus signals
# and calls into our model object.
self.submodules.slave = wishbone.Target(MyModelWB())
# The "wishbone.Tap" library component examines the bus at the slave port
# and displays the transactions on the console (<TRead...>/<TWrite...>).
self.submodules.tap = wishbone.Tap(self.slave.bus)
# Connect the master to the slave.
self.submodules.intercon = wishbone.InterconnectPointToPoint(
self.master.bus, self.slave.bus)
def wishbone_sim(efragment, master, end_simulation): peripheral = wishbone.Target(MyModelWB()) tap = wishbone.Tap(peripheral.bus) interconnect = wishbone.InterconnectPointToPoint(master.bus, peripheral.bus) def _end_simulation(s): s.interrupt = end_simulation(s) fragment = efragment \ + peripheral.get_fragment() \ + tap.get_fragment() \ + interconnect.get_fragment() \ + Fragment(sim=[_end_simulation]) sim = Simulator(fragment, Runner()) sim.run()
def main():
# The "wishbone.Initiator" library component runs our generator
# and manipulates the bus signals accordingly.
master = wishbone.Initiator(my_generator())
# Our slave.
slave = MyPeripheral()
# The "wishbone.Tap" library component examines the bus at the slave port
# and displays the transactions on the console (<TRead...>/<TWrite...>).
tap = wishbone.Tap(slave.bus)
# Connect the master to the slave.
intercon = wishbone.InterconnectPointToPoint(master.bus, slave.bus)
# A small extra simulation function to terminate the process when
# the initiator is done (i.e. our generator is exhausted).
def end_simulation(s):
s.interrupt = master.done
fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner())
sim.run()
def __init__(self):
self.submodules.phy_model = phy.PHY(8, debug=False)
self.submodules.mac_model = mac.MAC(self.phy_model,
debug=False,
loopback=False)
self.submodules.arp_model = arp.ARP(self.mac_model,
mac_address,
ip_address,
debug=False)
self.submodules.ip_model = ip.IP(self.mac_model,
mac_address,
ip_address,
debug=False,
loopback=False)
self.submodules.udp_model = udp.UDP(self.ip_model,
ip_address,
debug=False,
loopback=False)
self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model,
debug=False)
self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address,
ip_address, 100000)
self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
self.submodules.sram = wishbone.SRAM(1024)
self.submodules.interconnect = wishbone.InterconnectPointToPoint(
self.etherbone.master.bus, self.sram.bus)
# use sys_clk for each clock_domain
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
self.comb += [
self.cd_eth_rx.clk.eq(ClockSignal()),
self.cd_eth_rx.rst.eq(ResetSignal()),
self.cd_eth_tx.clk.eq(ClockSignal()),
self.cd_eth_tx.rst.eq(ResetSignal()),
]
def test_writer():
print("*** Testing writer")
trgen = SimActor(trgen_gen(), ("address_data", Source, [("a", BV(30)), ("d", BV(32))]))
writer = dma_wishbone.Writer()
g = DataFlowGraph()
g.add_connection(trgen, writer)
comp = CompositeActor(g)
peripheral = MyPeripheral()
tap = wishbone.Tap(peripheral.bus)
interconnect = wishbone.InterconnectPointToPoint(writer.bus, peripheral.bus)
def end_simulation(s):
s.interrupt = trgen.done and not s.rd(comp.busy)
fragment = comp.get_fragment() \
+ peripheral.get_fragment() \
+ tap.get_fragment() \
+ interconnect.get_fragment() \
+ Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner())
sim.run()
def test_reader():
print("*** Testing reader")
adrgen = SimActor(adrgen_gen(), ("address", Source, [("a", BV(30))]))
reader = dma_wishbone.Reader()
dumper = SimActor(dumper_gen(), ("data", Sink, [("d", BV(32))]))
g = DataFlowGraph()
g.add_connection(adrgen, reader)
g.add_connection(reader, dumper)
comp = CompositeActor(g)
peripheral = MyPeripheral()
interconnect = wishbone.InterconnectPointToPoint(reader.bus, peripheral.bus)
def end_simulation(s):
s.interrupt = adrgen.done and not s.rd(comp.busy)
fragment = comp.get_fragment() \
+ peripheral.get_fragment() \
+ interconnect.get_fragment() \
+ Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner())
sim.run()
def __init__(self):
pads = _TestPads()
self.submodules.dut = AD9xxx(pads, drive_fud=True)
self.submodules.initiator = wishbone.Initiator(_test_gen())
self.submodules.interconnect = wishbone.InterconnectPointToPoint(
self.initiator.bus, self.dut.bus)
def __init__(self, master): self.submodules.peripheral = wishbone.Target(MyModelWB()) self.submodules.tap = wishbone.Tap(self.peripheral.bus) self.submodules.interconnect = wishbone.InterconnectPointToPoint(master.bus, self.peripheral.bus)
