def __init__(self): pads = Signal(8) self.submodules.gp = Gpio(pads) self.comb += pads[4:].eq(pads[:4]) self.submodules.wb = Wishbone() self.submodules.dut = Master([ (self.gp, 0x00000100, 0xffffff00), # (self.dds, 0x00010000, 0xffff0000), (self.wb, 0x20000000, 0xe0000000), # (self.spi, 0x40000000, 0xe0000000), # (self.i2c, 0x60000000, 0xe0000000), ]) self.submodules.csrbanks = csrgen.BankArray( self, lambda name, mem: {"dut": 0}[name]) self.submodules.ini = csr.Initiator(_test_gen()) self.submodules.con = csr.Interconnect(self.ini.bus, self.csrbanks.get_buses()) #self.submodules.wbini = wishbone.Initiator(_test_gen_wb()) #self.submodules.wbtap = wishbone.Tap(self.dut.bus) #self.submodules.wbcon = wishbone.InterconnectPointToPoint( # self.wbini.bus, self.dut.bus) self.submodules.wbtg = wishbone.Target(wishbone.TargetModel()) self.submodules.wbtap = wishbone.Tap(self.wbtg.bus) self.submodules.wbic = wishbone.InterconnectPointToPoint( self.wb.bus, self.wbtg.bus)
def __init__(self, ng): g = DataFlowGraph() d = Dumper(layout) g.add_connection(ng, d) self.submodules.slave = wishbone.Target(SlaveModel()) self.submodules.intercon = wishbone.InterconnectPointToPoint( ng.wb, self.slave.bus) self.submodules.ca = CompositeActor(g)
def __init__(self): # The "wishbone.Initiator" library component runs our generator # and manipulates the bus signals accordingly. self.submodules.master = wishbone.Initiator(my_generator()) # The "wishbone.Target" library component examines the bus signals # and calls into our model object. self.submodules.slave = wishbone.Target(MyModelWB()) # The "wishbone.Tap" library component examines the bus at the slave port # and displays the transactions on the console (<TRead...>/<TWrite...>). self.submodules.tap = wishbone.Tap(self.slave.bus) # Connect the master to the slave. self.submodules.intercon = wishbone.InterconnectPointToPoint( self.master.bus, self.slave.bus)
def wishbone_sim(efragment, master, end_simulation): peripheral = wishbone.Target(MyModelWB()) tap = wishbone.Tap(peripheral.bus) interconnect = wishbone.InterconnectPointToPoint(master.bus, peripheral.bus) def _end_simulation(s): s.interrupt = end_simulation(s) fragment = efragment \ + peripheral.get_fragment() \ + tap.get_fragment() \ + interconnect.get_fragment() \ + Fragment(sim=[_end_simulation]) sim = Simulator(fragment, Runner()) sim.run()
def test_wishbone(): print("*** Wishbone test") # The "wishbone.Initiator" library component runs our generator # and manipulates the bus signals accordingly. master = wishbone.Initiator(my_generator()) # The "wishbone.Target" library component examines the bus signals # and calls into our model object. slave = wishbone.Target(MyModelWB()) # The "wishbone.Tap" library component examines the bus at the slave port # and displays the transactions on the console (<TRead...>/<TWrite...>). tap = wishbone.Tap(slave.bus) # Connect the master to the slave. intercon = wishbone.InterconnectPointToPoint(master.bus, slave.bus) # A small extra simulation function to terminate the process when # the initiator is done (i.e. our generator is exhausted). def end_simulation(s): s.interrupt = master.done fragment = autofragment.from_local() + Fragment(sim=[end_simulation]) sim = Simulator(fragment, Runner()) sim.run()
def __init__(self, master): self.submodules.peripheral = wishbone.Target(MyModelWB()) self.submodules.tap = wishbone.Tap(self.peripheral.bus) self.submodules.interconnect = wishbone.InterconnectPointToPoint(master.bus, self.peripheral.bus)