def __init__(self, period, width=6, clk=None): self.clk = Signal() if clk is None else clk self.value = CSRStatus(32) # # # self.clock_domains.cd_fmeter = ClockDomain(reset_less=True) self.comb += self.cd_fmeter.clk.eq(self.clk) # Period generation period_done = Signal() period_counter = Signal(32) self.comb += period_done.eq(period_counter == period) self.sync += \ If(period_done, period_counter.eq(0), ).Else( period_counter.eq(period_counter + 1) ) # Frequency measurement event_counter = ClockDomainsRenamer("fmeter")(GrayCounter(width)) gray_decoder = GrayDecoder(width) sampler = _Sampler(width) self.submodules += event_counter, gray_decoder, sampler self.specials += MultiReg(event_counter.q, gray_decoder.i) self.comb += [ event_counter.ce.eq(1), sampler.latch.eq(period_done), sampler.i.eq(gray_decoder.o), self.value.status.eq(sampler.o) ]
def __init__(self, link_layer, rx_clock_domain): self.aux_word_cnt = CSRStatus(64) self.aux_zword_cnt = CSRStatus(64) self.rt_word_cnt = CSRStatus(64) self.rt_zword_cnt = CSRStatus(64) self.update_link_stats = CSR() # # # aux_word = Signal() aux_zword = Signal() rt_word = Signal() rt_zword = Signal() sync = getattr(self.sync, rx_clock_domain) sync += [ aux_word.eq(link_layer.rx_aux_frame_perm), aux_zword.eq(link_layer.rx_aux_frame_perm & (link_layer.rx_aux_data == 0)), rt_word.eq(link_layer.rx_rt_frame_perm), rt_zword.eq(link_layer.rx_rt_frame_perm & (link_layer.rx_aux_data == 0)) ] for trigger, csr in [(aux_word, self.aux_word_cnt), (aux_zword, self.aux_zword_cnt), (rt_word, self.rt_word_cnt), (rt_zword, self.rt_zword_cnt)]: counter = ClockDomainsRenamer(rx_clock_domain)(GrayCounter(64)) decoder = GrayDecoder(64) self.submodules += counter, decoder counter.q.attr.add("no_retiming") self.specials += MultiReg(counter.q, decoder.i) self.comb += counter.ce.eq(trigger) self.sync += If(self.update_link_stats.re, csr.status.eq(decoder.o))
def __init__(self, measure_clock, measure_period, measure_width=6, counter_width=32): self.value = CSRStatus(counter_width) # # # # create measure clock domain self.clock_domains.cd_measure = ClockDomain(reset_less=True) self.comb += self.cd_measure.clk.eq(measure_clock) # mesure period period_done = Signal() period_counter = Signal(counter_width) self.comb += period_done.eq(period_counter == measure_period) self.sync += \ If(period_done, period_counter.eq(0), ).Else( period_counter.eq(period_counter + 1) ) # measurement event_counter = ClockDomainsRenamer("measure")( GrayCounter(measure_width)) gray_decoder = GrayDecoder(measure_width) sampler = Sampler(measure_width, counter_width) self.submodules += event_counter, gray_decoder, sampler self.specials += MultiReg(event_counter.q, gray_decoder.i) self.comb += [ event_counter.ce.eq(1), sampler.latch.eq(period_done), sampler.i.eq(gray_decoder.o), self.value.status.eq(sampler.value) ]
def __init__(self, platform): sys_clock_pads = platform.request("clk156") self.clock_domains.cd_sys = ClockDomain(reset_less=True) self.specials += Instance("IBUFGDS", i_I=sys_clock_pads.p, i_IB=sys_clock_pads.n, o_O=self.cd_sys.clk) sys_clk_freq = 156000000 self.comb += platform.request("sfp_tx_disable_n").eq(1) gtx = GTXReceiver(clock_pads=platform.request("sgmii_clock"), rx_pads=platform.request("sfp_rx"), sys_clk_freq=sys_clk_freq) self.submodules += gtx # PRBS checker checker = ClockDomainsRenamer("rx_clean")(CEInserter()( PRBSChecker(16))) self.submodules += checker self.sync.rx += [ checker.ce.eq(~gtx.decoders[0].k), checker.i[:8].eq(gtx.decoders[0].d), checker.i[8:].eq(gtx.decoders[1].d) ] error_accumulator = ClockDomainsRenamer("rx_clean")(GrayCounter(32)) self.submodules += error_accumulator error_bits = [checker.errors[i] for i in range(len(checker.errors))] self.comb += error_accumulator.ce.eq(reduce(or_, error_bits)) error_decoder = GrayDecoder(32) self.submodules += error_decoder self.specials += [ NoRetiming(error_accumulator.q), MultiReg(error_accumulator.q, error_decoder.i) ] # Wishbone target - I2C i2c_master = I2CMaster(platform.request("i2c")) self.submodules += i2c_master # Wishbone target - PRBS error count checker_wb = wishbone.Interface() self.sync += [ checker_wb.dat_r.eq(error_decoder.o), checker_wb.ack.eq(0), If(checker_wb.cyc & checker_wb.stb & ~checker_wb.ack, checker_wb.ack.eq(1)) ] # Wishbone master - Sequencer sequencer = Sequencer(get_i2c_program(sys_clk_freq)) self.submodules += sequencer # Wishbone master - UART bridge uart_phy = RS232PHY(platform.request("serial"), sys_clk_freq, 115200) bridge = WishboneStreamingBridge(uart_phy, sys_clk_freq) self.submodules += uart_phy, bridge # Wishbone interconnect interconnect = wishbone.InterconnectShared( [sequencer.bus, bridge.wishbone], [(lambda a: a[4] == 0, i2c_master.bus), (lambda a: a[4] == 1, checker_wb)], register=True) self.submodules += interconnect si5324_clock_router = Si5324ClockRouter(platform, sys_clk_freq) self.submodules += si5324_clock_router