def __init__(self, clk_freq, baud_rate):
self.submodules.rxcore = RX(clk_freq, baud_rate)
self.submodules.fifo = SyncFIFO(8, 1024)
self.comb += [self.fifo.din.eq(self.rxcore.data)]
self.submodules.fsm = FSM(reset_state='IDLE')
self.fsm.act(
'IDLE',
If(
self.rxcore.ready,
If(
self.fifo.writable,
self.fifo.we.eq(1),
),
self.rxcore.ack.eq(1),
NextState('READING'),
).Else(self.fifo.we.eq(0), ))
self.fsm.act(
'READING',
self.fifo.we.eq(0),
self.rxcore.ack.eq(0),
If(
~self.rxcore.ready,
NextState('IDLE'),
),
)
self.dout = self.fifo.dout
self.re = self.fifo.re
self.readable = self.fifo.readable
self.rx = self.rxcore.rx
self.io = {self.dout, self.re, self.readable, self.rx}
def __init__(self, width=14, N_points=16383, max_delay=16383):
self.submodules.robust = RobustAutolock(max_delay=max_delay)
self.submodules.fast = FastAutolock(width=width)
self.request_lock = CSRStorage()
self.autolock_mode = CSRStorage(2)
self.lock_running = CSRStatus()
self.comb += [
self.fast.request_lock.eq(self.request_lock.storage),
self.robust.request_lock.eq(self.request_lock.storage),
]
self.sync += [
If(
~self.request_lock.storage,
self.lock_running.status.eq(0),
),
If(
self.request_lock.storage
& self.fast.turn_on_lock
& (self.autolock_mode.storage == FAST_AUTOLOCK),
self.lock_running.status.eq(1),
),
If(
self.request_lock.storage
& self.robust.turn_on_lock
& (self.autolock_mode.storage == ROBUST_AUTOLOCK),
self.lock_running.status.eq(1),
),
]
def __init__(self, m):
"""Output a signal for a given time.
Args:
m: a ``counter_width`` counter :class:`Signal` that governs the output
times.
"""
self.m_start = Signal(counter_width)
self.m_stop = Signal(counter_width)
self.clear = Signal()
self.output = Signal()
# # #
self.stb_start = Signal()
self.stb_stop = Signal()
self.comb += [
self.stb_start.eq(m == self.m_start),
self.stb_stop.eq(m == self.m_stop),
]
self.sync += [
If(self.stb_start,
self.output.eq(1)).Else(If(self.stb_stop, self.output.eq(0))),
If(self.clear, self.output.eq(0)),
]
def __init__(self, a_in, b_in, y_out, cmd, err, NBITS):
# generics
self.NBITS = NBITS
# inputs
self.a_in = a_in
self.b_in = b_in
self.y_out = y_out
self.cmd = cmd
self.err = err
#internals
self.sum = Signal(NBITS + 1)
###
self.comb += [
If(
self.cmd == Commands.MIN, self.err.eq(0),
If(self.a_in < self.b_in, self.y_out.eq(self.a_in)).Else(
self.y_out.eq(self.b_in))).Elif(
self.cmd == Commands.MAX, self.err.eq(0),
If(self.a_in > self.b_in, self.y_out.eq(
self.a_in)).Else(self.y_out.eq(self.b_in))).Elif(
self.cmd == Commands.SUM, self.err.eq(0),
self.y_out.eq(self.a_in + self.b_in)).Elif(
self.cmd == Commands.AVG, self.err.eq(0),
self.sum.eq(self.a_in + self.b_in),
If(self.sum != 0,
self.y_out.eq(self.sum >> 1)).Else(
self.y_out.eq(self.sum))).Else(
self.err.eq(1))
]
def __init__(self, width):
self.run = Signal()
self.step = Signal(width - 1)
self.turn = Signal()
self.hold = Signal()
self.y = Signal((width, True))
self.trigger = Signal()
###
self.up = Signal()
turning = Signal()
dir = Signal()
self.comb += [
If(
self.run,
If(self.turn & ~turning,
self.up.eq(~dir)).Else(self.up.eq(dir)),
).Else(self.up.eq(1))
]
self.sync += [
self.trigger.eq(self.turn & self.up),
turning.eq(self.turn),
dir.eq(self.up),
If(~self.run, self.y.eq(0)).Elif(
~self.hold,
If(
self.up,
self.y.eq(self.y + self.step),
).Else(self.y.eq(self.y - self.step), ),
),
]
def __init__(self, syncword):
self.sink = stream.Endpoint([
("data", 8),
])
self.source = stream.Endpoint([
("data", 8),
])
###
self.submodules.fsm = FSM(reset_state="DATA")
self.fsm.act(
"DATA",
self.source.payload.data.eq(self.sink.payload.data),
self.source.stb.eq(self.sink.stb),
self.sink.ack.eq(self.source.ack),
If(
self.sink.stb & self.sink.ack & self.sink.eop,
NextState("SYNC"),
),
)
self.fsm.act(
"SYNC",
self.source.payload.data.eq(syncword),
self.source.stb.eq(1),
self.sink.ack.eq(0),
If(
self.source.stb & self.source.ack,
NextState("DATA"),
),
)
def __init__(self):
self.cfu_bus = Record(cfu_bus_minimized_layout)
self.cfu_cen = Signal()
self.cpu_cen = Signal()
self.submodules.fsm = fsm = FSM(reset_state="CPU_ENABLED")
fsm.act(
"CPU_ENABLED",
self.cpu_cen.eq(1),
self.cfu_cen.eq(0),
# If CPU has prepared a command, enable CFU
If(
self.cfu_bus.cmd.valid,
self.cfu_cen.eq(1),
NextState("CFU_ENABLED"),
))
fsm.act(
"CFU_ENABLED",
self.cfu_cen.eq(1),
self.cpu_cen.eq(1),
# Disable CPU if CFU is calculating response
If(
~self.cfu_bus.rsp.valid & ~self.cfu_bus.cmd.valid,
self.cpu_cen.eq(0),
# Enable CPU and disable CFU if CPU received a response and has no next command
If(
self.cfu_bus.cmd.ready,
self.cpu_cen.eq(1),
NextState("CPU_ENABLED"),
)))
def __init__(self, reset, pmt_trigger, rf_trigger, photon, clock):
# inputs
self.reset = reset
self.photon = photon
# outputs
self.pmt_trigger = pmt_trigger
self.rf_trigger = rf_trigger
self.clock = clock
# internal signals
self.photon_reg = Signal(5)
###
self.sync += [
If(
self.reset.data == 1,
self.clock.eq(0),
).Else(self.clock.eq(self.clock + 1)),
If(self.photon.valid,
self.photon_reg.eq(self.photon.data)).Else(
self.photon_reg.eq(self.photon_reg))
]
self.comb += [
If((self.clock == TIME_RES - 1), self.rf_trigger.eq(1),
self.pmt_trigger.eq(0)).Elif(
(self.clock == TIME_RES - 1 - self.photon_reg),
self.rf_trigger.eq(0),
self.pmt_trigger.eq(1)).Else(self.rf_trigger.eq(0),
self.pmt_trigger.eq(0))
]
def __init__(self, bus_wishbone=None, bus_csr=None):
if bus_wishbone is None:
bus_wishbone = wishbone.Interface()
self.wishbone = bus_wishbone
if bus_csr is None:
bus_csr = csr_bus.Interface()
self.csr = bus_csr
self.ack = Signal()
self.en = Signal()
# # #
self.comb += [
self.csr.dat_w.eq(self.wishbone.dat_w),
self.wishbone.dat_r.eq(self.csr.dat_r)
]
count = Signal(8)
fsm = FSM(reset_state="WRITE-READ")
self.submodules += fsm
fsm.act(
"WRITE-READ",
If(
self.wishbone.cyc & self.wishbone.stb,
self.csr.adr.eq(self.wishbone.adr),
self.csr.we.eq(self.wishbone.we),
self.en.eq(1),
NextState("ACK"),
))
fsm.act(
"ACK",
If(self.wishbone.we | self.ack, self.wishbone.ack.eq(1),
NextState("WRITE-READ")))
def cross_connect(gpio, chains):
state_names = ["force"] + ["di%i" % i for i in range(len(gpio.i))]
states = [1, gpio.i]
signal_names = ["zero"]
signals = Array([0])
for n, c in chains:
for s in c.state_out:
states.append(s)
state_names.append("%s_%s" % (n, s.backtrace[-1][0]))
for s in c.signal_out:
signals.append(s)
name = s.backtrace[-1][0]
signal_names.append("%s_%s" % (n, name))
sig = CSRStatus(len(s), name=name)
clr = CSR(name="%s_clr" % name)
max = CSRStatus(len(s), name="%s_max" % name)
min = CSRStatus(len(s), name="%s_min" % name)
# setattr(c, sig.name, sig)
setattr(c, clr.name, clr)
setattr(c, max.name, max)
setattr(c, min.name, min)
c.comb += sig.status.eq(s)
c.sync += If(clr.re | (max.status < s), max.status.eq(s))
c.sync += If(clr.re | (min.status > s), min.status.eq(s))
states = Cat(states)
state = Signal(len(states))
gpio.comb += state.eq(states)
gpio.state = CSRStatus(len(state))
gpio.state_clr = CSR()
gpio.sync += [
If(
gpio.state_clr.re,
gpio.state.status.eq(0),
).Else(gpio.state.status.eq(gpio.state.status | state), )
]
# connect gpio output to "doi%i_en"
for i, s in enumerate(gpio.o):
csr = CSRStorage(len(state), name="do%i_en" % i)
setattr(gpio, csr.name, csr)
gpio.sync += s.eq((state & csr.storage) != 0)
# connect state ins to "%s_en" and signal ins to "%s_sel"
for n, c in chains:
for s in c.state_in:
csr = CSRStorage(len(state), name="%s_en" % s.backtrace[-1][0])
setattr(c, csr.name, csr)
c.sync += s.eq((state & csr.storage) != 0)
for s in c.signal_in:
csr = CSRStorage(bits_for(len(signals) - 1),
name="%s_sel" % s.backtrace[-1][0])
setattr(c, csr.name, csr)
c.sync += s.eq(signals[csr.storage])
return state_names, signal_names
def __init__(self, m, phy_ref, phy_sig):
"""Define the gateware to gate & latch inputs."""
self.clear = Signal()
self.triggered = Signal()
n_fine = len(phy_ref.fine_ts)
full_timestamp_width = counter_width + n_fine
self.ref_ts = Signal(full_timestamp_width)
self.sig_ts = Signal(full_timestamp_width)
# In mu
self.gate_start = Signal(full_timestamp_width)
self.gate_stop = Signal(full_timestamp_width)
# # #
self.got_ref = Signal()
# Absolute gate times, calculated when we get the reference event
abs_gate_start = Signal(full_timestamp_width)
abs_gate_stop = Signal(full_timestamp_width)
t_ref = Signal(full_timestamp_width)
self.comb += t_ref.eq(Cat(phy_ref.fine_ts, m))
self.sync += [
If(
phy_ref.stb_rising,
self.got_ref.eq(1),
self.ref_ts.eq(t_ref),
abs_gate_start.eq(self.gate_start + t_ref),
abs_gate_stop.eq(self.gate_stop + t_ref),
),
If(self.clear, self.got_ref.eq(0), self.triggered.eq(0)),
]
past_window_start = Signal()
before_window_end = Signal()
triggering = Signal()
t_sig = Signal(full_timestamp_width)
self.comb += [
t_sig.eq(Cat(phy_sig.fine_ts, m)),
past_window_start.eq(t_sig >= abs_gate_start),
before_window_end.eq(t_sig <= abs_gate_stop),
triggering.eq(past_window_start & before_window_end),
]
self.sync += [
If(
phy_sig.stb_rising & ~self.triggered & triggering,
self.triggered.eq(triggering),
self.sig_ts.eq(t_sig),
)
]
def __init__(self, hit_channels, time, reset, clock):
# parameters
# inputs
self.hit_channels = hit_channels
self.reset = reset
self.clock = clock
# outputs
self.time = time
# internal signals
self.meta_reg1 = Signal(self.NB_INPUTS)
self.meta_reg2 = Signal(self.NB_INPUTS)
self.edge_reg = Signal(self.NB_INPUTS)
self.edge_detect = Signal(self.NB_INPUTS)
self.hit_time_regs = Array(
Signal(TIME_RES) for a in range(self.NB_INPUTS))
self.time_reg = Signal(TIME_RES)
####
# edge detector with meta-stability removal register chain
self.sync += [
self.meta_reg1.eq(self.hit_channels),
self.meta_reg2.eq(self.meta_reg1),
self.edge_reg.eq(self.meta_reg2),
]
for i in range(self.NB_INPUTS):
self.sync += [
If(
self.edge_detect[i], # pulse detected
self.hit_time_regs[i].eq(
self.clock) # update hit register
).Elif(
self.reset.data == 1,
self.hit_time_regs[i].eq(0),
).Elif(
self.hit_time_regs[i] != 0, # reset hit register
self.hit_time_regs[i].eq(0))
]
self.comb += [
self.time_reg.eq(self.hit_time_regs[0]
| self.hit_time_regs[1])
]
self.comb += [
self.reset.ready.eq(1),
self.time.data.eq(self.time_reg),
self.edge_detect.eq(~self.edge_reg
& self.meta_reg2), # edge detection
# output logic
If(self.time_reg != 0,
self.time.valid.eq(1)).Else(self.time.valid.eq(0))
]
def __init__(self, platform):
clk12 = platform.request("clk12")
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
reset_delay = Signal(max=1024)
self.comb += [
self.cd_por.clk.eq(clk12),
self.cd_sys.clk.eq(clk12),
self.cd_sys.rst.eq(reset_delay != 1023)
]
self.sync.por += \
If(reset_delay != 1023,
reset_delay.eq(reset_delay + 1)
)
self.submodules.dec = SyncDecoder(8, 3 * 7)
self.comb += [
self.dec.data.eq(platform.request("din")),
self.dec.wck.eq(platform.request("wck")),
self.dec.bck.eq(platform.request("bck")),
]
self.submodules.packager = Packager(0x47)
serial = platform.request("fast_serial")
self.submodules.tx = FastSerialTX(serial)
self.comb += self.tx.sink.payload.port.eq(1)
self.comb += [
self.dec.source.connect(self.packager.sink),
self.packager.source.connect(self.tx.sink),
]
# 96.000 MHz pll and /10 for mclk
self.mclk = platform.request("mclk")
pll_out = Signal()
self.specials.pll = Instance("pll",
i_clock_in=ClockSignal("sys"),
o_clock_out=pll_out)
self.clock_domains.cd_pll = ClockDomain(reset_less=True)
self.comb += self.cd_pll.clk.eq(pll_out)
self.counter = Signal(max=5)
self.sync.pll += [
If(self.counter >= 4,
self.counter.eq(0),
self.mclk.eq(~self.mclk),
).Else(
self.counter.eq(self.counter + 1),
)
]
def __init__(self, n_bits, n_words):
self.n_bits = n_bits
self.n_words = n_words
self.data = Signal()
self.wck = Signal()
self.source = stream.Endpoint([
("data", n_bits),
])
###
self.word = Signal(n_bits)
self.bit = Signal(max=n_bits)
self.word_num = Signal(max=n_words + 1)
self.last_bit = (self.bit == 0) & (self.word_num > 0)
self.sync += self.word.eq(self.word << 1 | self.data)
self.sync += self.source.stb.eq(self.last_bit)
self.sync += self.source.eop.eq(self.word_num == 1)
self.comb += self.source.payload.data.eq(self.word)
self.sync += \
If(self.wck,
self.bit.eq(n_bits - 2),
self.word_num.eq(n_words),
).Elif(self.last_bit,
self.bit.eq(n_bits - 1),
self.word_num.eq(self.word_num - 1),
).Else(
self.bit.eq(self.bit - 1),
)
def __init__(self, freq_width=32, **kwargs):
Filter.__init__(self, **kwargs)
width = len(self.y)
self.amp = CSRStorage(width)
self.freq = CSRStorage(freq_width)
self.phase = Signal(width)
self.sync_phase = Signal()
z = Signal(freq_width)
stop = Signal()
self.sync += [
stop.eq(self.freq.storage == 0),
If(stop | self.sync_phase, z.eq(0)).Else(z.eq(z + self.freq.storage)),
]
self.submodules.cordic = Cordic(
width=width + 1,
stages=width + 1,
guard=2,
eval_mode="pipelined",
cordic_mode="rotate",
func_mode="circular",
)
self.comb += [
self.phase.eq(z[-len(self.phase) :]),
self.cordic.xi.eq(self.amp.storage + self.x),
self.cordic.zi.eq(self.phase << 1),
self.y.eq(self.cordic.xo >> 1),
]
def __init__(self, width=14):
# pid is not started directly by `request_lock` signal. Instead, `request_lock`
# queues a run that is then started when the ramp is at the zero target position
self.request_lock = Signal()
self.turn_on_lock = Signal()
self.sweep_value = Signal((width, True))
self.sweep_step = Signal(width)
self.sweep_up = Signal()
self.target_position = CSRStorage(width)
target_position_signed = Signal((width, True))
self.comb += [target_position_signed.eq(self.target_position.storage)]
self.sync += [
If(
~self.request_lock,
self.turn_on_lock.eq(0),
).Else(
self.turn_on_lock.
eq((self.sweep_value >= target_position_signed -
(self.sweep_step >> 1))
& (self.sweep_value <= target_position_signed + 1 +
(self.sweep_step >> 1))
# and if the ramp is going up (because this is when a
# spectrum is recorded)
& (self.sweep_up)), ),
]
def calculate_i(self):
self.ki = CSRStorage(self.coeff_width)
self.reset = CSRStorage()
ki_signed = Signal((self.coeff_width, True))
self.comb += [ki_signed.eq(self.ki.storage)]
self.ki_mult = Signal((1 + self.width + self.coeff_width, True))
self.comb += [self.ki_mult.eq((self.error * ki_signed) >> 4)]
int_reg_width = self.width + self.coeff_width + 4
extra_width = int_reg_width - self.width
self.int_reg = Signal((int_reg_width, True))
self.int_sum = Signal((int_reg_width + 1, True))
self.int_out = Signal((self.width, True))
self.comb += [
self.int_sum.eq(self.ki_mult + self.int_reg),
self.int_out.eq(self.int_reg >> extra_width)
]
max_pos_extra = (self.max_pos << extra_width)
max_neg_extra = (-1 * max_pos_extra) - 1
self.sync += [
If(self.reset.storage, self.int_reg.eq(0)).Elif(
self.int_sum > max_pos_extra, # positive saturation
self.int_reg.eq(max_pos_extra)).Elif(
self.int_sum < max_neg_extra, # negative saturation
self.int_reg.eq(max_neg_extra)).Else(
self.int_reg.eq(self.int_sum))
]
def __init__(self):
p = fb.fil[0]['fxqc']
# -------------- Get generics -----------------------------------------
# p = {}
# # new Key , Key 1 und 2 in fxqc_dict, default value
# p_list = [['WI', 'QI','W', 16],
# ['WO', 'QO','W', 16],
# ['WA', 'QA','W', 31],
# ['WC', 'QC','W', 16],
# ['b', 'QC','b', [1,1,1]]
# ]
#Automatic : p['WA'] = p['WC'] + p['WI'] =- 1
# for l in p_list:
# try:
# p[l[0]] = fxqc_dict[l[1]][l[2]]
# except (KeyError, TypeError) as e:
# logger.warning("Error [{0}][{1}]:\n{2}".format(l[1],l[2],e))
# p[l[0]] = l[3]
# ------------- Define I/Os -------------------------------------------
ovfl_o = p['QO']['ovfl']
quant_o = p['QO']['quant']
WI = p['QI']['W']
WO = p['QO']['W']
# saturation logic doesn't make much sense with a FIR filter, this is
# just for demonstration
if ovfl_o == 'wrap':
WA = p['QA']['W']
else:
WA = p['QA']['W'] + 1 # add one guard bit
self.i = Signal((WI, True)) # input signal
self.o = Signal((WO, True)) # output signal
MIN_o = -1 << (WO - 1)
MAX_o = -MIN_o - 1
self.response = []
###
muls = []
src = self.i
for c in p['QC']['b']:
sreg = Signal((WI, True)) # registers for input signal
self.sync += sreg.eq(src)
src = sreg
muls.append(c * sreg)
sum_full = Signal((WA, True))
self.sync += sum_full.eq(reduce(
add, muls)) # sum of multiplication products
if ovfl_o == 'wrap':
self.comb += self.o.eq(sum_full >>
(WA - WO)) # rescale for output width
else:
self.comb += \
If(sum_full[WA-2:] == 0b10,
self.o.eq(MIN_o)
).Elif(sum_full[WA-2:] == 0b01,
self.o.eq(MAX_o)
).Else(self.o.eq(sum_full >> (WA-WO-1))
)
def __init__(self, platform):
serial = platform.request("fast_serial")
clk12 = platform.request("clk12")
self.clock_domains.cd_sys = ClockDomain()
if True:
self.specials.pll = Instance("pll_test",
i_clock_in=clk12,
o_clock_out=self.cd_sys.clk)
else:
self.comb += self.cd_sys.clk.eq(clk12)
self.clock_domains.cd_por = ClockDomain(reset_less=True)
reset_delay = Signal(max=1024)
self.comb += [
self.cd_por.clk.eq(self.cd_sys.clk),
self.cd_sys.rst.eq(reset_delay != 1023)
]
self.sync.por += If(reset_delay != 1023,
reset_delay.eq(reset_delay + 1))
self.submodules.tx = FastSerialTX(serial)
self.submodules.packager = Packager(0x47)
self.comb += self.packager.source.connect(self.tx.sink)
self.comb += self.tx.sink.payload.port.eq(1)
counter = Signal(5)
self.comb += [
self.packager.sink.stb.eq(1),
self.packager.sink.payload.data.eq(counter),
self.packager.sink.eop.eq(counter == 2**counter.nbits - 1)
]
self.sync += [
If(self.packager.sink.stb & self.packager.sink.ack,
counter.eq(counter + 1)),
]
debug = platform.request("debug")
self.comb += [
debug.eq(Cat(serial.clk, serial.di, serial.cts)),
]
def calc_index(pos, sin, port, acc=True, zero=False):
block = If(pos < 128, [
port.adr.eq(pos),
sin.eq(sin + port.dat_r) if acc else sin.eq(port.dat_r)
]).Elif(pos < 256, [
port.adr.eq(127 - (pos - 128)),
sin.eq(sin + port.dat_r) if acc else sin.eq(port.dat_r)
])
if zero:
block = block.Elif(pos == 256, [sin.eq(0)])
block = block.Elif(pos < 512 - 128, [
port.adr.eq(512 - 128 - pos),
sin.eq(sin + port.dat_r) if acc else sin.eq(port.dat_r)
]).Else([
port.adr.eq(512 - pos - 1),
sin.eq(sin + port.dat_r) if acc else sin.eq(port.dat_r)
])
return block
def __init__(self):
self.hc = Signal(bits_sign=10)
self.vc = Signal(bits_sign=10)
self.hsync = Signal()
self.vsync = Signal()
self.color = Color6()
self.comb += trinary(self.hc < VGA.hpulse, self.hsync.eq(0), self.hsync.eq(1))
self.comb += trinary(self.vc < VGA.hpulse, self.vsync.eq(0), self.vsync.eq(1))
self.sync += If(self.hc < VGA.hpixels - 1, [
self.hc.eq(self.hc + 1)
]).Else([
self.hc.eq(0),
If(self.vc < VGA.vlines - 1, [
self.vc.eq(self.vc + 1)
]).Else([
self.vc.eq(0)
])
])
def __init__(self):
"""Create a test harness for the :class:`TriggeredInputGater`."""
self.m = Signal(14)
self.rst = Signal()
self.sync += [self.m.eq(self.m + 1), If(self.rst, self.m.eq(0))]
self.submodules.phy_ref = MockPhy(self.m)
self.submodules.phy_sig = MockPhy(self.m)
core = TriggeredInputGater(self.m, self.phy_ref, self.phy_sig)
self.submodules.core = core
self.comb += core.clear.eq(self.rst)
def calculate_error_signal(self):
self.setpoint = CSRStorage(self.width)
setpoint_signed = Signal((self.width, True))
self.comb += [setpoint_signed.eq(self.setpoint.storage)]
self.error = Signal((self.width + 1, True))
self.comb += [
If(self.running,
self.error.eq(self.input - self.setpoint.storage)).Else(
self.error.eq(0))
]
def __init__(self, plat, superunit):
self.garbage = Cat([plat.request("user_led") for _ in range(3)])
self.bad_led = plat.request("user_led")
self.good_led = plat.request("user_led")
self.submodules += superunit
self.comb += [
[g.eq(0) for g in self.garbage]
]
self.sync += [
If(self.good_led == 0,
self.good_led.eq(superunit.o_success & superunit.o_over))
.Else(
self.good_led.eq(1)),
If(self.bad_led == 0,
self.bad_led.eq(~superunit.o_success & superunit.o_over))
.Else(
self.bad_led.eq(0))
]
def __init__(self, pads):
self.sink = stream.Endpoint([
("data", 8),
("port", 1),
])
###
cts = Signal()
self.specials += MultiReg(pads.cts, cts)
di = Signal(reset=1)
self.comb += pads.di.eq(di)
tx_reg = Signal(9)
tx_bit = Signal(max=10)
self.sync += [
self.sink.ack.eq(0),
If(
self.sink.stb & cts & (tx_bit == 0) & ~self.sink.ack,
tx_reg.eq(Cat(self.sink.payload.data, self.sink.payload.port)),
tx_bit.eq(9),
di.eq(0),
).Elif(
tx_bit > 0,
tx_bit.eq(tx_bit - 1),
di.eq(tx_reg[0]),
tx_reg.eq(tx_reg[1:]),
If(
tx_bit == 1,
self.sink.ack.eq(1),
),
).Else(di.eq(1), )
]
self.comb += [
pads.clk.eq(~ClockSignal()),
]
def __init__(self, n):
# Output
self.o = Signal(max=n, reset=0)
###
self.sync += [
If(self.o == n - 1,
self.o.eq(0))
.Else(
self.o.eq(self.o + 1)
)
]
def __init__(self, input_bit, max_delay):
self.delay = Signal(bits_for(max_delay))
self.restart = Signal()
self.writing_data_now = Signal()
self.input = Signal((input_bit, True))
self.output = Signal((input_bit, True))
# this ensures that counter overflows / underflows correctly
assert max_delay == (2**(bits_for(max_delay)) - 1)
self.mem_rdport, self.mem_wrport = create_memory(
self, input_bit, max_delay, "dynamic_delay_mem")
# register all the ports
self.specials += [self.mem_rdport, self.mem_wrport]
self.counter = Signal(bits_for(max_delay))
self.counter_delayed = Signal((bits_for(max_delay)))
negative_delay = 1
self.sync += [
If(self.restart, self.counter.eq(0)).Else(
If(self.writing_data_now, self.counter.eq(self.counter + 1))),
]
self.comb += [
self.mem_wrport.we.eq(self.writing_data_now),
self.mem_wrport.adr.eq(self.counter),
self.mem_wrport.dat_w.eq(self.input),
self.mem_rdport.adr.eq(self.counter_delayed),
self.counter_delayed.eq(self.counter - self.delay +
negative_delay),
self.mem_rdport.adr.eq(self.counter_delayed),
If(self.counter < self.delay - negative_delay,
self.output.eq(0)).Else(self.output.eq(
self.mem_rdport.dat_r), ),
]
def __init__(self, vga, sin_t, col_t):
pos1 = Signal(bits_sign=9)
pos3 = Signal(bits_sign=9)
tpos1 = Signal(bits_sign=9)
tpos2 = Signal(bits_sign=9)
tpos3 = Signal(bits_sign=9)
tpos4 = Signal(bits_sign=9)
index = Signal(bits_sign=6)
count = Signal()
self.specials.col_t = Memory(4, 256, init=col_t)
self.specials.sin_t = Memory(32, 512, init=sin_t)
sin_p = self.sin_t.get_port(async_read=True)
col_p = self.col_t.get_port(async_read=True)
self.specials += sin_p
self.specials += col_p
self.ios = {sin_p.adr, sin_p.dat_r, col_p.adr, col_p.dat_r}
sin = Signal(bits_sign=(32, True))
self.sync += If(vga.hc < VGA.hpixels - 1, [
If((vga.hc >= VGA.hbp) & (vga.hc < VGA.hfp), [
tpos1.eq(tpos1 + 5),
tpos2.eq(tpos2 + 3)
])
]).Else([
If(vga.vc < VGA.vlines - 1, [
If((vga.vc >= VGA.vbp) & (vga.vc < VGA.vfp), [
tpos1.eq(pos1 + 5),
tpos2.eq(3),
tpos3.eq(tpos3 + 1),
tpos4.eq(tpos4 + 3)
])
]).Else([
pos1.eq(pos1 + 9),
pos3.eq(pos3 + 8),
tpos4.eq(0),
tpos3.eq(0),
count.eq(count + 1)
])
])
self.sync += If((vga.vc >= VGA.vbp) & (vga.vc < VGA.vfp), [
If((vga.hc >= VGA.hbp) & (vga.hc < VGA.hfp), [
calc_index(tpos1, sin, sin_p, acc=False, zero=True),
calc_index(tpos2, sin, sin_p),
calc_index(tpos3, sin, sin_p),
calc_index(tpos4, sin, sin_p),
index.eq(sin >> 4),
col_p.adr.eq(index),
Cat(vga.color.g1, vga.color.g0, vga.color.r1, vga.color.r0).eq(col_p.dat_r)
]).Else(vga.color.black())
]).Else(vga.color.black())
def __init__(self, width=14, N_points=16383, max_delay=16383):
self.restart = Signal()
self.writing_data_now = Signal()
self.input = Signal((width, True))
self.delay_value = Signal(bits_for(N_points))
sum_value_bits = bits_for(((2**width) - 1) * N_points)
self.sum_value = Signal((sum_value_bits, True))
delayed_sum = Signal((sum_value_bits, True))
current_sum_diff = Signal((sum_value_bits + 1, True))
self.output = Signal.like(current_sum_diff)
self.submodules.delayer = DynamicDelay(sum_value_bits,
max_delay=max_delay)
self.sync += [
If(
self.restart,
self.sum_value.eq(0),
).Else(
If(
self.writing_data_now,
# not at start
self.sum_value.eq(self.sum_value + self.input),
))
]
self.comb += [
self.delayer.writing_data_now.eq(self.writing_data_now),
self.delayer.restart.eq(self.restart),
self.delayer.delay.eq(self.delay_value),
self.delayer.input.eq(self.sum_value),
delayed_sum.eq(self.delayer.output),
current_sum_diff.eq(self.sum_value - delayed_sum),
self.output.eq(current_sum_diff),
]
def migen_body(self, template):
inp = template.add_pa_in_port('inp', DOptional(DInt()))
trigger = template.add_pa_in_port('trigger', DOptional(DInt()))
out = template.add_pa_out_port('out', DInt())
# Declare input and output ports always happy to receive/transmit data
self.comb += (
inp.ready.eq(1),
trigger.ready.eq(1),
out.ready.eq(1),
)
commander_fsm = FSM(reset_state="IDLE")
self.submodules.commander_fsm = commander_fsm
commander_fsm.act("IDLE", If(inp.valid == 1, NextState("LOADING")))
commander_fsm.act(
"LOADING",
If(trigger.valid & trigger.data == 1, NextState("RETURN")).Else(
NextValue(out.data, out.data + inp.data), ))
commander_fsm.act("RETURN", NextValue(out.valid, 1), NextState("IDLE"))
