def decode_sequence(seq): output = [] dut = line_coding.Decoder() def pump(): for w in seq: yield dut.input.eq(w) yield if (yield dut.k): output.append(Control((yield dut.d))) else: output.append((yield dut.d)) yield if (yield dut.k): output.append(Control((yield dut.d))) else: output.append((yield dut.d)) run_simulation(dut, pump()) return output[1:]
def __init__(self, lsb_first=False): self.rx_en = Signal() self.rx_data = Signal(8) self.seen_valid_ci = Signal() self.seen_config_reg = Signal() self.config_reg = Signal(16) self.submodules.decoder = code_8b10b.Decoder(lsb_first=lsb_first) # SGMII Speed Adaptation self.sgmii_speed = Signal(2) self.sample_en = Signal() # # # config_reg_lsb = Signal(8) load_config_reg_lsb = Signal() load_config_reg_msb = Signal() self.sync += [ self.seen_config_reg.eq(0), If(load_config_reg_lsb, config_reg_lsb.eq(self.decoder.d)), If(load_config_reg_msb, self.config_reg.eq(Cat(config_reg_lsb, self.decoder.d)), self.seen_config_reg.eq(1)) ] first_preamble_byte = Signal() self.comb += self.rx_data.eq( Mux(first_preamble_byte, 0x55, self.decoder.d)) # Timer for SGMII data rates timer = Signal(max=1000) timer_en = Signal() self.sync += [ If( ~timer_en | (timer == 0), If(self.sgmii_speed == 0b00, timer.eq(99)).Elif( self.sgmii_speed == 0b01, timer.eq(9)).Elif( self.sgmii_speed == 0b10, timer.eq(0))).Elif(timer_en, timer.eq(timer - 1)) ] # Speed adaptation self.comb += self.sample_en.eq(self.rx_en & (timer == 0)) fsm = FSM() self.submodules += fsm fsm.act( "START", If( self.decoder.k, If(self.decoder.d == K(28, 5), NextState("K28_5")), If(self.decoder.d == K(27, 7), self.rx_en.eq(1), timer_en.eq(1), first_preamble_byte.eq(1), NextState("DATA")))) fsm.act( "K28_5", NextState("START"), If( ~self.decoder.k, If((self.decoder.d == D(21, 5)) | (self.decoder.d == D(2, 2)), self.seen_valid_ci.eq(1), NextState("CONFIG_REG_LSB")), If( (self.decoder.d == D(5, 6)) | (self.decoder.d == D(16, 2)), # idle self.seen_valid_ci.eq(1), NextState("START")), )) fsm.act( "CONFIG_REG_LSB", If( self.decoder.k, If(self.decoder.d == K(27, 7), self.rx_en.eq(1), timer_en.eq(1), first_preamble_byte.eq(1), NextState("DATA")).Else( NextState("START") # error )).Else(load_config_reg_lsb.eq(1), NextState("CONFIG_REG_MSB"))) fsm.act("CONFIG_REG_MSB", If(~self.decoder.k, load_config_reg_msb.eq(1)), NextState("START")) fsm.act( "DATA", If(self.decoder.k, NextState("START")).Else(self.rx_en.eq(1), timer_en.eq(1)))
def __init__(self, lsb_first=False): self.rx_en = Signal() self.rx_data = Signal(8) self.seen_valid_ci = Signal() self.seen_config_reg = Signal() self.config_reg = Signal(16) self.submodules.decoder = code_8b10b.Decoder(lsb_first=lsb_first) # # # config_reg_lsb = Signal(8) load_config_reg_lsb = Signal() load_config_reg_msb = Signal() self.sync += [ self.seen_config_reg.eq(0), If(load_config_reg_lsb, config_reg_lsb.eq(self.decoder.d)), If(load_config_reg_msb, self.config_reg.eq(Cat(config_reg_lsb, self.decoder.d)), self.seen_config_reg.eq(1) ) ] first_preamble_byte = Signal() self.comb += self.rx_data.eq(Mux(first_preamble_byte, 0x55, self.decoder.d)) fsm = FSM() self.submodules += fsm fsm.act("START", If(self.decoder.k, If(self.decoder.d == K(28, 5), NextState("K28_5") ), If(self.decoder.d == K(27, 7), self.rx_en.eq(1), first_preamble_byte.eq(1), NextState("DATA") ) ) ) fsm.act("K28_5", NextState("START"), If(~self.decoder.k, If((self.decoder.d == D(21, 5)) | (self.decoder.d == D(2, 2)), self.seen_valid_ci.eq(1), NextState("CONFIG_REG_LSB") ), If((self.decoder.d == D(5, 6)) | (self.decoder.d == D(16, 2)), # idle self.seen_valid_ci.eq(1), NextState("START") ), ) ) fsm.act("CONFIG_REG_LSB", If(self.decoder.k, If(self.decoder.d == K(27, 7), self.rx_en.eq(1), first_preamble_byte.eq(1), NextState("DATA") ).Else( NextState("START") # error ) ).Else( load_config_reg_lsb.eq(1), NextState("CONFIG_REG_MSB") ) ) fsm.act("CONFIG_REG_MSB", If(~self.decoder.k, load_config_reg_msb.eq(1) ), NextState("START") ) fsm.act("DATA", If(self.decoder.k, NextState("START") ).Else( self.rx_en.eq(1) ) )