def __init__(self, sdram_controller_type="minicon", **kwargs): platform = kasli.Platform() platform.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 2.5 [current_design]", ]) SoCSDRAM.__init__(self, platform, clk_freq=125*1000000, cpu_reset_address=0x400000, **kwargs) self.submodules.crg = _CRG(platform) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/self.clk_freq) self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_controller_type, sdram_module.geom_settings, sdram_module.timing_settings) self.csr_devices.append("ddrphy") if not self.integrated_rom_size: spiflash_pads = platform.request("spiflash2x") spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=5, div=2) self.config["SPIFLASH_PAGE_SIZE"] = 256 self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000 self.flash_boot_address = 0x450000 self.register_rom(self.spiflash.bus, 16*1024*1024) self.csr_devices.append("spiflash")
def __init__(self, sdram_controller_type="minicon", with_spiflash=False, **kwargs): platform = afc3v1.Platform() SoCSDRAM.__init__(self, platform, clk_freq=125000000, **kwargs) self.submodules.crg = _CRG(platform) self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.) self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41J512M8(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_controller_type, sdram_module.geom_settings, sdram_module.timing_settings) self.csr_devices.append("ddrphy") self.submodules.si570_oen = gpio.GPIOIn(platform.request( "si570_en", 0)) self.csr_devices.append("si570_oen") if not self.integrated_rom_size or with_spiflash: spiflash_pads = platform.request("spiflash") spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=11, div=2, endianness=self.cpu.endianness, dw=self.cpu_dw) self.config["SPIFLASH_PAGE_SIZE"] = 256 self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000 self.csr_devices.append("spiflash") if with_spiflash: self.add_wb_slave(self.mem_map["spiflash"], 16 * 1024 * 1024, self.spiflash.bus) if not self.integrated_rom_size: self.flash_boot_address = 0x350000 self.register_rom(self.spiflash.bus, 16 * 1024 * 1024)
def __init__(self, sdram_controller_type="minicon", hw_rev="v1.0", **kwargs): platform = kasli.Platform(hw_rev=hw_rev) SoCSDRAM.__init__(self, platform, clk_freq=125e6 * 15.25 / 16, cpu_reset_address=0x400000, **kwargs) self.submodules.crg = _CRG(platform) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / self.clk_freq) self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_controller_type, sdram_module.geom_settings, sdram_module.timing_settings) self.csr_devices.append("ddrphy") if not self.integrated_rom_size: spiflash_pads = platform.request("spiflash2x") spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=5, div=2) self.config["SPIFLASH_PAGE_SIZE"] = 256 self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000 self.flash_boot_address = 0x450000 self.register_rom(self.spiflash.bus, 16 * 1024 * 1024) self.csr_devices.append("spiflash")