def __init__(self, use_ext_clock=False, csr_data_width=def_csr_data_width, csr_addr_width=def_csr_addr_width): ps = jesd204b.common.JESD204BPhysicalSettings(l=self.nLanes, m=4, n=16, np=16) ts = jesd204b.common.JESD204BTransportSettings(f=2, s=1, k=16, cs=0) jesd_settings = jesd204b.common.JESD204BSettings(ps, ts, did=0x5a, bid=0x5) self.submodules.crg = JESDConfig(use_ext_clock=use_ext_clock) if use_ext_clock: self.clock_domains.cd_ext = ClockDomain() refclk = self.crg.refclk refclk_freq = self.crg.refclk_freq linerate = self.crg.linerate sys_clk_freq = self.crg.fabric_freq self.jesd_pads_txp = Signal(self.nLanes, name="jesd_txp") self.jesd_pads_txn = Signal(self.nLanes, name="jesd_txn") self.dac_sync = Signal() self.jref = self.crg.jref self.csr_devices = ["crg", "control"] phys = [] for i in range(self.nLanes): gtxq = jesdphy.gtx.GTXQuadPLL(refclk, refclk_freq, linerate) self.submodules += gtxq phy = jesdphy.JESD204BPhyTX(gtxq, phyPad(self.jesd_pads_txp[i], self.jesd_pads_txn[i]), sys_clk_freq, transceiver="gtx") phys.append(phy) self.submodules.core = jesdc.JESD204BCoreTX(phys, jesd_settings, converter_data_width=64) self.submodules.control = jesdc.JESD204BCoreTXControl(self.core) self.core.register_jsync(self.dac_sync) self.core.register_jref(self.jref) self.csr_master = csr_bus.Interface(data_width=csr_data_width, address_width=csr_addr_width) self.submodules.csrbankarray = csr_bus.CSRBankArray( self, self.map_csr_dev, data_width=csr_data_width, address_width=csr_addr_width) self.submodules.csrcon = csr_bus.Interconnect( self.csr_master, self.csrbankarray.get_buses())
def do_finalize(self): registered_mems = {regions[0] for regions in self._memory_regions} # Wishbone self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters, self._wb_slaves.get_interconnect_slaves(), register=True) # CSR self.submodules.csrbankarray = csr_bus.CSRBankArray(self, self.get_csr_dev_address, data_width=self.csr_data_width, address_width=self.csr_address_width) self.submodules.csrcon = csr_bus.Interconnect( self.wishbone2csr.csr, self.csrbankarray.get_buses()) for name, csrs, mapaddr, rmap in self.csrbankarray.banks: self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs) for name, memory, mapaddr, mmap in self.csrbankarray.srams: self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory) for name, constant in self.csrbankarray.constants: self._constants.append(((name + "_" + constant.name).upper(), constant.value.value)) for name, value in sorted(self.config.items(), key=itemgetter(0)): self._constants.append(("CONFIG_" + name.upper(), value)) # Interrupts for nr, name in enumerate(self.interrupt_devices): self.comb += self.cpu.interrupt[nr].eq(getattr(self, name).ev.irq)
def __init__(self): self.submodules.id = DummyID() self.submodules.csrbanks = csr_bus.CSRBankArray( self, lambda name, mem: 0) self.submodules.sys2csr = Sys2CSR() self.submodules.csrcon = csr_bus.Interconnect( self.sys2csr.csr, self.csrbanks.get_buses()) self.sys = self.sys2csr.sys
def do_finalize(self): # CSR self.submodules.csrbankarray = csr_bus.CSRBankArray( self, self.get_csr_dev_address, data_width=self.csr_data_width, address_width=self.csr_address_width) self.submodules.csrcon = csr_bus.Interconnect( self.axi2csr.csr, self.csrbankarray.get_buses()) for name, csrs, mapaddr, rmap in self.csrbankarray.banks: self.add_csr_region( name, (self.mem_map["csr"] + 0x800 * mapaddr), self.csr_data_width, csrs) for name, memory, mapaddr, mmap in self.csrbankarray.srams: self.add_csr_region( "{}_{}".format(name, memory.name_override), (self.mem_map["csr"] + 0x800 * mapaddr), self.csr_data_width, memory) for name, constant in self.csrbankarray.constants: self._constants.append( (("_".join([name, constant.name]).upper(), constant.value.value))) for name, value in sorted(self.config.items(), key=itemgetter(0)): self._constants.append(("CONFIG_" + name.upper(), value)) # Interrupts for n, name in enumerate(self.interrupt_devices): self.comb += self.ps7.interrupt[n].eq(getattr(self, name).ev.irq) # AXI: FIXME: add InterconnectShared support slaves = self._axi_slaves.get_interconnect_slaves() if len(slaves) > 2: raise NotImplementedError("only P2P is supported") self.submodules += axi.InterconnectPointToPoint( self.ps7.m_axi_gp1, slaves[0][1]) if len(slaves) == 2: self.submodules += axi.InterconnectPointToPoint( self.ps7.m_axi_gp0, slaves[1][1])
def test_axi2csr(data_width): dut = AXI2CSR(bus_csr=csr_bus.Interface(data_width=data_width)) dut.submodules.sram = csr_bus.SRAM( 0x100, 0, bus=csr_bus.Interface(data_width=data_width)) dut.submodules += csr_bus.Interconnect(dut.csr, [dut.sram.bus]) write_aw = partial(dut.bus.write_aw, size=burst_size(dut.bus.data_width // 8), len_=0, burst=Burst.fixed) write_w = dut.bus.write_w read_b = dut.bus.read_b write_ar = partial(dut.bus.write_ar, size=burst_size(dut.bus.data_width // 8), len_=0, burst=Burst.fixed) read_r = dut.bus.read_r w_mon = partial(csr_w_mon, dut.csr) def testbench_axi2csr(): i = dut.bus def aw_channel(): assert (yield i.aw.ready) == 1 yield from write_aw(0x01, 0x00) yield from write_aw(0x02, 0x04) yield from write_aw(0x03, 0x08) yield from write_aw(0x04, 0x0c) yield from write_aw(0x05, 0x40) def w_channel(): yield from write_w(0, 0x11, strb=1) yield from write_w(0, 0x22, strb=1) yield from write_w(0, 0x33, strb=1) yield from write_w(0, 0x44, strb=1) yield from write_w(0, 0x11223344) def b_channel(): assert attrgetter_b((yield from read_b())) == (0x01, okay) assert attrgetter_b((yield from read_b())) == (0x02, okay) assert attrgetter_b((yield from read_b())) == (0x03, okay) assert attrgetter_b((yield from read_b())) == (0x04, okay) assert attrgetter_b((yield from read_b())) == (0x05, okay) def ar_channel(): # ensure data was actually written assert attrgetter_csr_w_mon((yield from w_mon())) == (0x00, 0x11) assert attrgetter_csr_w_mon((yield from w_mon())) == (0x01, 0x22) assert attrgetter_csr_w_mon((yield from w_mon())) == (0x02, 0x33) assert attrgetter_csr_w_mon((yield from w_mon())) == (0x03, 0x44) if data_width == 8: assert attrgetter_csr_w_mon((yield from w_mon())) == (0x10, 0x44) elif data_width == 16: assert attrgetter_csr_w_mon((yield from w_mon())) == (0x10, 0x3344) # ok, read it now yield from write_ar(0x11, 0x00) yield from write_ar(0x22, 0x04) yield from write_ar(0x33, 0x08) yield from write_ar(0x44, 0x0c) yield from write_ar(0x55, 0x40) def r_channel(): assert attrgetter_r((yield from read_r())) == (0x11, 0x11, okay, 1) assert attrgetter_r((yield from read_r())) == (0x22, 0x22, okay, 1) assert attrgetter_r((yield from read_r())) == (0x33, 0x33, okay, 1) assert attrgetter_r((yield from read_r())) == (0x44, 0x44, okay, 1) if data_width == 8: assert attrgetter_r((yield from read_r())) == (0x55, 0x44, okay, 1) elif data_width == 16: assert attrgetter_r((yield from read_r())) == (0x55, 0x3344, okay, 1) return [ aw_channel(), w_channel(), b_channel(), r_channel(), ar_channel(), ] run_simulation(dut, testbench_axi2csr(), vcd_name=file_tmp_folder("test_axi2csr.vcd"))
def __init__(self, platform): csr_map = { "dna": 28, "xadc": 29, "gpio_n": 30, "gpio_p": 31, "fast_a": 0, "fast_b": 1, "slow_a": 2, "slow_b": 3, "slow_c": 4, "slow_d": 5, "scopegen": 6, "noise": 7, } self.submodules.analog = PitayaAnalog(platform.request("adc"), platform.request("dac")) self.submodules.xadc = XADC(platform.request("xadc")) sys_double = ClockDomainsRenamer("sys_double") for i in range(4): pwm = platform.request("pwm", i) ds = sys_double(DeltaSigma(width=15)) self.comb += pwm.eq(ds.out) setattr(self.submodules, "ds%i" % i, ds) exp = platform.request("exp") self.submodules.gpio_n = Gpio(exp.n) self.submodules.gpio_p = Gpio(exp.p) leds = Cat(*(platform.request("user_led", i) for i in range(8))) self.comb += leds.eq(self.gpio_n.o) self.submodules.dna = DNA(version=2) s, c = 25, 18 self.submodules.fast_a = FastChain(14, s, c) self.submodules.fast_b = FastChain(14, s, c) sys_slow = ClockDomainsRenamer("sys_slow") self.submodules.slow_a = sys_slow(SlowChain(16, s, c)) self.slow_a.iir.interval.value.value *= 15 self.submodules.slow_b = sys_slow(SlowChain(16, s, c)) self.slow_b.iir.interval.value.value *= 15 self.submodules.slow_c = sys_slow(SlowChain(16, s, c)) self.slow_c.iir.interval.value.value *= 15 self.submodules.slow_d = sys_slow(SlowChain(16, s, c)) self.slow_d.iir.interval.value.value *= 15 self.submodules.scopegen = ScopeGen(s) #self.submodules.noise = LFSRGen(s) self.submodules.noise = XORSHIFTGen(s) self.state_names, self.signal_names = cross_connect( self.gpio_n, [ ("fast_a", self.fast_a), ("fast_b", self.fast_b), ("slow_a", self.slow_a), ("slow_b", self.slow_b), ("slow_c", self.slow_c), ("slow_d", self.slow_d), ("scopegen", self.scopegen), ("noise", self.noise), ]) self.comb += [ self.scopegen.trigger.eq(self.gpio_p.i[0]), self.fast_a.adc.eq(self.analog.adc_a), self.fast_b.adc.eq(self.analog.adc_b), self.analog.dac_a.eq(self.fast_a.dac), self.analog.dac_b.eq(self.fast_b.dac), self.slow_a.adc.eq(self.xadc.adc[0] << 4), self.ds0.data.eq(self.slow_a.dac), self.slow_b.adc.eq(self.xadc.adc[1] << 4), self.ds1.data.eq(self.slow_b.dac), self.slow_c.adc.eq(self.xadc.adc[2] << 4), self.ds2.data.eq(self.slow_c.dac), self.slow_d.adc.eq(self.xadc.adc[3] << 4), self.ds3.data.eq(self.slow_d.dac), ] self.submodules.csrbanks = csr_bus.CSRBankArray( self, lambda name, mem: csr_map[name if mem is None else name + "_" + mem.name_override]) self.submodules.sys2csr = Sys2CSR() self.submodules.csrcon = csr_bus.Interconnect( self.sys2csr.csr, self.csrbanks.get_buses()) self.submodules.syscdc = SysCDC() self.comb += self.syscdc.target.connect(self.sys2csr.sys)
def init_submodules( self, width, signal_width, coeff_width, chain_factor_bits, platform ): sys_double = ClockDomainsRenamer("sys_double") self.submodules.logic = LinienLogic(chain_factor_width=chain_factor_bits) self.submodules.analog = PitayaAnalog( platform.request("adc"), platform.request("dac") ) self.submodules.xadc = XADC(platform.request("xadc")) for i in range(4): pwm = platform.request("pwm", i) ds = sys_double(DeltaSigma(width=15)) self.comb += pwm.eq(ds.out) setattr(self.submodules, "ds%i" % i, ds) exp = platform.request("exp") self.submodules.gpio_n = Gpio(exp.n) self.submodules.gpio_p = Gpio(exp.p) leds = Cat(*(platform.request("user_led", i) for i in range(8))) self.comb += leds.eq(self.gpio_n.o) self.submodules.dna = DNA(version=2) self.submodules.fast_a = FastChain( width, signal_width, coeff_width, self.logic.mod, offset_signal=self.logic.chain_a_offset_signed, ) self.submodules.fast_b = FastChain( width, signal_width, coeff_width, self.logic.mod, offset_signal=self.logic.chain_b_offset_signed, ) sys_slow = ClockDomainsRenamer("sys_slow") sys_double = ClockDomainsRenamer("sys_double") max_decimation = 16 self.submodules.decimate = sys_double(Decimate(max_decimation)) self.clock_domains.cd_decimated_clock = ClockDomain() decimated_clock = ClockDomainsRenamer("decimated_clock") self.submodules.slow = decimated_clock(SlowChain()) self.submodules.scopegen = ScopeGen(signal_width) self.state_names, self.signal_names = cross_connect( self.gpio_n, [ ("fast_a", self.fast_a), ("fast_b", self.fast_b), ("slow", self.slow), ("scopegen", self.scopegen), ("logic", self.logic), ("robust", self.logic.autolock.robust), ], ) csr_map = { "dna": 28, "xadc": 29, "gpio_n": 30, "gpio_p": 31, "fast_a": 0, "fast_b": 1, "slow": 2, "scopegen": 6, "noise": 7, "logic": 8, } self.submodules.csrbanks = csr_bus.CSRBankArray( self, lambda name, mem: csr_map[ name if mem is None else name + "_" + mem.name_override ], ) self.submodules.sys2csr = Sys2CSR() self.submodules.csrcon = csr_bus.Interconnect( self.sys2csr.csr, self.csrbanks.get_buses() ) self.submodules.syscdc = SysCDC() self.comb += self.syscdc.target.connect(self.sys2csr.sys)
def __init__(self, platform): csr_map = { "dna": 28, "xadc": 29, "gpio_n": 30, "gpio_p": 31, "fast_a": 0, "fast_b": 1, "slow": 2, #"slow_a": 2, "slow_b": 3, "slow_c": 4, "slow_d": 5, "scopegen": 6, "noise": 7, 'root': 8 } chain_factor_bits = 8 self.submodules.root = PIDCSR(chain_factor_width=chain_factor_bits) self.submodules.analog = PitayaAnalog(platform.request("adc"), platform.request("dac")) self.submodules.xadc = XADC(platform.request("xadc")) sys_double = ClockDomainsRenamer("sys_double") for i in range(4): pwm = platform.request("pwm", i) ds = sys_double(DeltaSigma(width=15)) self.comb += pwm.eq(ds.out) setattr(self.submodules, "ds%i" % i, ds) exp = platform.request("exp") self.submodules.gpio_n = Gpio(exp.n) self.submodules.gpio_p = Gpio(exp.p) leds = Cat(*(platform.request("user_led", i) for i in range(8))) self.comb += leds.eq(self.gpio_n.o) self.submodules.dna = DNA(version=2) signal_width, coeff_width = 25, 25 width = 14 s = signal_width - width self.submodules.fast_a = FastChain( width, signal_width, coeff_width, self.root.mod, offset_signal=self.root.chain_a_offset_signed) self.submodules.fast_b = FastChain( width, signal_width, coeff_width, self.root.mod, offset_signal=self.root.chain_b_offset_signed) sys_slow = ClockDomainsRenamer("sys_slow") sys_double = ClockDomainsRenamer("sys_double") max_decimation = 16 self.submodules.decimate = sys_double(Decimate(max_decimation)) self.clock_domains.cd_decimated_clock = ClockDomain() decimated_clock = ClockDomainsRenamer('decimated_clock') self.submodules.slow = decimated_clock(SlowChain()) self.submodules.scopegen = ScopeGen(signal_width) self.state_names, self.signal_names = cross_connect( self.gpio_n, [("fast_a", self.fast_a), ("fast_b", self.fast_b), ("slow", self.slow), ("scopegen", self.scopegen), ("root", self.root)]) # now, we combine the output of the two paths, with a variable # factor each. mixed = Signal( (2 + ((signal_width + 1) + self.root.chain_a_factor.size), True)) self.comb += [ If( self.root.dual_channel.storage, mixed.eq((self.root.chain_a_factor.storage * self.fast_a.dac) + (self.root.chain_b_factor.storage * self.fast_b.dac) + (self.root.combined_offset_signed << (chain_factor_bits + s)))).Else( mixed.eq(self.fast_a.dac << chain_factor_bits)) ] mixed_limited = Signal((signal_width, True)) self.comb += [ self.root.limit_error_signal.x.eq(mixed >> chain_factor_bits), mixed_limited.eq(self.root.limit_error_signal.y) ] pid_out = Signal((width, True)) self.comb += [ self.root.pid.input.eq(mixed_limited), pid_out.eq(self.root.pid.pid_out >> s) ] fast_outs = list(Signal((width + 4, True)) for channel in (0, 1)) for channel, fast_out in enumerate(fast_outs): self.comb += fast_out.eq( Mux(self.root.control_channel.storage == channel, pid_out, 0) + Mux(self.root.mod_channel.storage == channel, self.root.mod.y, 0) + Mux(self.root.sweep_channel.storage == channel, self.root.sweep.y, 0) + Mux(self.root.sweep_channel.storage == channel, self.root.out_offset_signed, 0)) slow_pid_out = Signal((width, True)) self.comb += slow_pid_out.eq(self.slow.output) slow_out = Signal((width + 2, True)) self.comb += slow_out.eq( slow_pid_out + Mux(self.root.sweep_channel.storage == ANALOG_OUT0, self.root.sweep.y, 0) + Mux(self.root.sweep_channel.storage == ANALOG_OUT0, self.root.out_offset_signed, 0)) slow_out_shifted = Signal(15) self.sync += slow_out_shifted.eq( # ds0 apparently has 16 bit, but only allowing positive # values --> "15 bit"? (self.slow.limit.y << 1) + (1 << 14)) self.comb += [ self.scopegen.gpio_trigger.eq(self.gpio_p.i[0]), self.scopegen.sweep_trigger.eq(self.root.sweep.sweep.trigger), self.fast_a.adc.eq(self.analog.adc_a), self.fast_b.adc.eq(self.analog.adc_b), self.root.limit_fast1.x.eq(fast_outs[0]), self.root.limit_fast2.x.eq(fast_outs[1]), self.analog.dac_a.eq(self.root.limit_fast1.y), self.analog.dac_b.eq(self.root.limit_fast2.y), # SLOW OUT self.slow.input.eq(self.root.control_signal >> s), self.decimate.decimation.eq(self.root.slow_decimation.storage), self.cd_decimated_clock.clk.eq(self.decimate.output), self.slow.limit.x.eq(slow_out), self.ds0.data.eq(slow_out_shifted), self.root.slow_value.status.eq(self.slow.limit.y), #self.slow_b.adc.eq(self.xadc.adc[1] << 4), #self.ds1.data.eq(self.slow_b.dac), #self.slow_c.adc.eq(self.xadc.adc[2] << 4), #self.ds2.data.eq(self.slow_c.dac), #self.slow_d.adc.eq(self.xadc.adc[3] << 4), #self.ds3.data.eq(self.slow_d.dac), ] self.submodules.csrbanks = csr_bus.CSRBankArray( self, lambda name, mem: csr_map[name if mem is None else name + "_" + mem.name_override]) self.submodules.sys2csr = Sys2CSR() self.submodules.csrcon = csr_bus.Interconnect( self.sys2csr.csr, self.csrbanks.get_buses()) self.submodules.syscdc = SysCDC() self.comb += self.syscdc.target.connect(self.sys2csr.sys)