def __init__(self, platform, firmware_ram_size=0xa000, firmware_filename=None, **kwargs): clk_freq = 80*1000000 SDRAMSoC.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, sdram_controller_settings=LASMIconSettings(with_bandwidth=True), **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.submodules.dna = dna.DNA() self.submodules.git_info = git_info.GitInfo() self.submodules.platform_info = platform_info.PlatformInfo("minispartan6"[:8], self.__class__.__name__[:8]) if not self.integrated_main_ram_size: self.submodules.ddrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), AS4C16M16(clk_freq)) self.register_sdram_phy(self.ddrphy) self.submodules.spiflash = spiflash.SpiFlash( platform.request("spiflash2x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div) self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): SDRAMSoC.__init__(self, platform, clk_freq=100*1000000, integrated_rom_size=0x8000, sdram_controller_settings=sdram_controller_settings, **kwargs) self.submodules.crg = _CRG(platform) if not self.integrated_main_ram_size: self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), IS42S16160(self.clk_freq)) self.register_sdram_phy(self.sdrphy)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): clk_freq = 80*1000000 SDRAMSoC.__init__(self, platform, clk_freq, cpu_reset_address=0x60000, sdram_controller_settings=sdram_controller_settings, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) if not self.integrated_main_ram_size: self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), MT48LC4M16(clk_freq)) self.register_sdram_phy(self.sdrphy) if not self.integrated_rom_size: self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6) self.flash_boot_address = 0x70000 self.register_rom(self.spiflash.bus)
sdram_timing = sdram.TimingSettings( tRP=ns(15), tRCD=ns(15), tWR=ns(14), tWTR=2, tREFI=ns(64*1000*1000/4096, False), tRFC=ns(66), req_queue_size=8, read_time=32, write_time=16 ) sdram_pads = plat.request("sdram") sdram_clk = plat.request("sdram_clock") sdrphy = gensdrphy.GENSDRPHY(sdram_pads) # This sets CL to 2 during LMR done on 1st cycle sdram_pads.a.reset = 1<<5 s = MiniconTB(sdrphy, sdrphy.dfi, sdram_geom, sdram_timing, pads=sdram_pads, sdram_clk=sdram_clk) extra_files = ["sdram_model/mt48lc4m16a2.v"] if not isfile(extra_files[0]): print("ERROR: You need to download Micron Verilog simulation model for MT48LC4M16A2 and put it in sdram_model/mt48lc4m16a2.v") print("File can be downloaded from this URL: http://www.micron.com/-/media/documents/products/sim%20model/dram/dram/4054mt48lc4m16a2.zip") sys.exit(1) with Simulator(s, MyTopLevel("top.vcd", clk_period=int(1/0.08)), icarus.Runner(extra_files=extra_files, keep_files=True)) as sim: sim.run(5000)