def gen_model(cap=0.16e-6, ind=0.16e-6, res=0.1, dt=0.01e-6, real_type=RealType.FixedPoint): # declare model m = MixedSignalModel('model', dt=dt, real_type=real_type) m.add_analog_input('v_in') m.add_analog_output('v_out') m.add_digital_input('clk') m.add_digital_input('rst') # declare system of equations m.add_analog_state('i_ind', 10) # TODO: can this be tightened down a bit? v_l = AnalogSignal('v_l') v_r = AnalogSignal('v_r') eqns = [ Deriv(m.i_ind) == v_l / ind, Deriv(m.v_out) == m.i_ind / cap, v_r == m.i_ind * res, m.v_in == m.v_out + v_l + v_r ] m.add_eqn_sys(eqns, clk=m.clk, rst=m.rst) BUILD_DIR.mkdir(parents=True, exist_ok=True) model_file = BUILD_DIR / 'model.sv' m.compile_to_file(VerilogGenerator(), filename=model_file) return model_file
def main(): tau = 1e-6 dt = 0.1e-6 model = MixedSignalModel('model', dt=dt) model.add_analog_input('v_in') model.add_analog_output('v_out', init=1.23) model.add_eqn_sys([Deriv(model.v_out) == (model.v_in - model.v_out)/tau]) model.compile_and_print(VerilogGenerator())
def __init__(self, name='filter', res=1e3, cap=1e-9, dt=0.1e-6): # call the super constructor super().__init__(name, dt=dt) # define IOs self.add_analog_input('v_in') self.add_analog_output('v_out') # define dynamics self.add_eqn_sys( [Deriv(self.v_out) == (self.v_in - self.v_out) / (res * cap)])
def main(): dt = 0.01e-6 cap = 0.16e-6 ind = 0.16e-6 res = 0.1 model = MixedSignalModel('model', dt=dt) model.add_analog_input('v_in') model.add_analog_output('v_out') model.add_analog_state('i_ind', 100) v_l = AnalogSignal('v_l') v_r = AnalogSignal('v_r') eqns = [ Deriv(model.i_ind) == v_l / ind, Deriv(model.v_out) == model.i_ind / cap, v_r == model.i_ind * res, model.v_in == model.v_out + v_l + v_r ] model.add_eqn_sys(eqns) model.compile_and_print(VerilogGenerator())
def main(cap=0.16e-6, ind=0.16e-6, res=0.1): print('Running model generator...') # parse command line arguments parser = ArgumentParser() parser.add_argument('-o', '--output', type=str) parser.add_argument('--dt', type=float) args = parser.parse_args() # create the model model = MixedSignalModel('rlc', AnalogInput('v_in'), AnalogOutput('v_out'), dt=args.dt) model.add_analog_state('i_ind', 100) # internal variables v_l = AnalogSignal('v_l') v_r = AnalogSignal('v_r') # define dynamics eqns = [ Deriv(model.i_ind) == v_l / ind, Deriv(model.v_out) == model.i_ind / cap, v_r == model.i_ind * res, model.v_in == model.v_out + v_l + v_r ] model.add_eqn_sys(eqns) # define probes #model.add_probe(model.i_ind) # determine the output filename filename = os.path.join(get_full_path(args.output), f'{model.module_name}.sv') print('Model will be written to: ' + filename) # generate the model model.compile_to_file(VerilogGenerator(), filename)
def gen_model(tau, dt, real_type): model = MixedSignalModel('model', dt=dt, real_type=real_type) model.add_analog_input('v_in') model.add_analog_output('v_out') model.add_digital_input('clk') model.add_digital_input('rst') model.add_eqn_sys([Deriv(model.v_out) == (model.v_in - model.v_out) / tau], clk=model.clk, rst=model.rst) BUILD_DIR.mkdir(parents=True, exist_ok=True) model_file = BUILD_DIR / 'model.sv' model.compile_to_file(VerilogGenerator(), filename=model_file) return model_file
def main(): tau = 1e-6 dt = 0.1e-6 model = MixedSignalModel('model', dt=dt) model.add_analog_input('v_in') model.add_analog_output('v_out') model.add_digital_input('ctrl') model.add_eqn_sys([ Deriv( model.v_out) == eqn_case([0, 1 / tau], [model.ctrl]) * model.v_in - model.v_out / tau ]) model.compile_and_print(VerilogGenerator())
def main(): tau_det_fast = 1e-9 tau_det_slow = 360e-9 dt = 4.6e-9 m = MixedSignalModel('model', dt=dt) m.add_analog_input('v_in') m.add_analog_output('v_out') m.bind_name('in_gt_out', m.v_in > m.v_out) # detector dynamics m.add_eqn_sys([ Deriv(m.v_out) == eqn_case([0, 1 / tau_det_fast], [m.in_gt_out]) * (m.v_in - m.v_out) - (m.v_out / tau_det_slow) ]) m.compile_and_print(VerilogGenerator())
def main(tau=1e-6): print('Running model generator...') # parse command line arguments parser = ArgumentParser() parser.add_argument('-o', '--output', type=str) parser.add_argument('--dt', type=float) args = parser.parse_args() # create the model model = MixedSignalModel('filter', DigitalInput('ctrl'), AnalogInput('v_in'), AnalogOutput('v_out'), dt=args.dt) # define dynamics model.add_eqn_sys([ Deriv(model.v_out) == eqn_case([0, 1/tau], [model.ctrl])*model.v_in - model.v_out/tau ]) # determine the output filename filename = os.path.join(get_full_path(args.output), f'{model.module_name}.sv') print('Model will be written to: ' + filename) # generate the model model.compile_to_file(VerilogGenerator(), filename)
def gen_model(tau_f=1e-9, tau_s=100e-9, dt=10e-9, real_type=RealType.FixedPoint): m = MixedSignalModel('model', dt=dt, real_type=real_type) m.add_analog_input('v_in') m.add_analog_output('v_out') m.add_digital_input('clk') m.add_digital_input('rst') m.bind_name('in_gt_out', m.v_in > m.v_out) # detector dynamics eqns = [ Deriv(m.v_out) == eqn_case([0, 1 / tau_f], [m.in_gt_out]) * (m.v_in - m.v_out) - (m.v_out / tau_s) ] m.add_eqn_sys(eqns, clk=m.clk, rst=m.rst) BUILD_DIR.mkdir(parents=True, exist_ok=True) model_file = BUILD_DIR / 'model.sv' m.compile_to_file(VerilogGenerator(), filename=model_file) return model_file