def __init__(self, func, deco, name, srcfile, srcline, *args, **kwargs):
calls = deco.calls
self.func = func
self.args = args
self.kwargs = kwargs
self.__doc__ = func.__doc__
callinfo = _getCallInfo()
self.callinfo = callinfo
self.modctxt = callinfo.modctxt
self.callername = callinfo.name
self.symdict = None
self.sigdict = {}
self.memdict = {}
self.name = self.__name__ = name
# flatten, but keep BlockInstance objects
self.subs = _flatten(func(*args, **kwargs))
self._verifySubs()
self._updateNamespaces()
self.verilog_code = self.vhdl_code = None
self.sim = None
if hasattr(deco, 'verilog_code'):
self.verilog_code = _UserVerilogCode(deco.verilog_code, self.symdict, func.__name__,
func, srcfile, srcline)
if hasattr(deco, 'vhdl_code'):
self.vhdl_code = _UserVhdlCode(deco.vhdl_code, self.symdict, func.__name__,
func, srcfile, srcline)
if hasattr(deco, 'verilog_instance'):
self.verilog_code = _UserVerilogInstance(deco.vhdl_instance, self.symdict, func.__name__,
func, srcfile, srcline)
if hasattr(deco, 'vhdl_instance'):
self.vhdl_code = _UserVhdlInstance(deco.vhdl_instance, self.symdict, func.__name__,
func, srcfile, srcline)
self._config_sim = {'trace': False}
def __init__(self, func, deco, name, srcfile, srcline, *args, **kwargs):
calls = deco.calls
self.func = func
self.args = args
self.kwargs = kwargs
self.__doc__ = func.__doc__
callinfo = _getCallInfo()
self.callinfo = callinfo
self.modctxt = callinfo.modctxt
self.callername = callinfo.name
self.symdict = None
self.sigdict = {}
self.memdict = {}
self.name = self.__name__ = name
# flatten, but keep BlockInstance objects
self.subs = _flatten(func(*args, **kwargs))
self._verifySubs()
self._updateNamespaces()
self.verilog_code = self.vhdl_code = None
self.sim = None
if hasattr(deco, 'verilog_code'):
self.verilog_code = _UserVerilogCode(deco.verilog_code, self.symdict, func.__name__,
func, srcfile, srcline)
if hasattr(deco, 'vhdl_code'):
self.vhdl_code = _UserVhdlCode(deco.vhdl_code, self.symdict, func.__name__,
func, srcfile, srcline)
if hasattr(deco, 'verilog_instance'):
self.verilog_code = _UserVerilogInstance(deco.vhdl_instance, self.symdict, func.__name__,
func, srcfile, srcline)
if hasattr(deco, 'vhdl_instance'):
self.vhdl_code = _UserVhdlInstance(deco.vhdl_instance, self.symdict, func.__name__,
func, srcfile, srcline)
self._config_sim = {'trace': False}
