def visit_Module(self, node):
_AnalyzeBlockVisitor.visit_Module(self, node)
if self.tree.kind == _kind.SIMPLE_ALWAYS_COMB:
for n in self.tree.outputs:
s = self.tree.sigdict[n]
s._driven = "wire"
for n in self.tree.outmems:
m = _getMemInfo(self.tree.symdict[n])
m._driven = "wire"
def visit_Module(self, node):
_AnalyzeBlockVisitor.visit_Module(self, node)
if self.tree.kind == _kind.SIMPLE_ALWAYS_COMB:
for n in self.tree.outputs:
s = self.tree.sigdict[n]
s._driven = "wire"
for n in self.tree.outmems:
m = _getMemInfo(self.tree.symdict[n])
m._driven = "wire"
def getName(self, node):
addSignBit = False
isMixedExpr = (not node.signed) and (self.context == _context.SIGNED)
n = node.id
if n == 'False':
s = "1'b0"
elif n == 'True':
s = "1'b1"
elif n == 'None':
s = "'bz"
elif n in self.tree.vardict:
addSignBit = isMixedExpr
s = n
elif n in self.tree.argnames:
assert n in self.tree.symdict
addSignBit = isMixedExpr
s = n
elif n in self.tree.symdict:
obj = self.tree.symdict[n]
if isinstance(obj, bool):
s = "%s" % int(obj)
elif isinstance(obj, (int, long)):
s = self.IntRepr(obj)
elif isinstance(obj, _Signal):
addSignBit = isMixedExpr
s = str(obj)
elif _isMem(obj):
m = _getMemInfo(obj)
assert m.name
s = m.name
elif isinstance(obj, EnumItemType):
s = obj._toVerilog()
elif type(obj) in (ClassType, TypeType) and issubclass(
obj, Exception):
s = n
else:
self.raiseError(node, _error.UnsupportedType,
"%s, %s" % (n, type(obj)))
else:
raise AssertionError("name ref: %s" % n)
if addSignBit:
self.write("$signed({1'b0, ")
self.write(s)
if addSignBit:
self.write("})")
def getName(self, node):
addSignBit = False
isMixedExpr = (not node.signed) and (self.context == _context.SIGNED)
n = node.id
if n == 'False':
s = "1'b0"
elif n == 'True':
s = "1'b1"
elif n == 'None':
s = "'bz"
elif n in self.tree.vardict:
addSignBit = isMixedExpr
s = n
elif n in self.tree.argnames:
assert n in self.tree.symdict
addSignBit = isMixedExpr
s = n
elif n in self.tree.symdict:
obj = self.tree.symdict[n]
if isinstance(obj, bool):
s = "%s" % int(obj)
elif isinstance(obj, (int, long)):
s = self.IntRepr(obj)
elif isinstance(obj, _Signal):
addSignBit = isMixedExpr
s = str(obj)
elif _isMem(obj):
m = _getMemInfo(obj)
assert m.name
s = m.name
elif isinstance(obj, EnumItemType):
s = obj._toVerilog()
elif type(obj) in (ClassType, TypeType) and issubclass(obj, Exception):
s = n
else:
self.raiseError(node, _error.UnsupportedType, "%s, %s" % (n, type(obj)))
else:
raise AssertionError("name ref: %s" % n)
if addSignBit:
self.write("$signed({1'b0, ")
self.write(s)
if addSignBit:
self.write("})")
def getName(self, node):
n = node.id
if PY2 and n in ('True', 'False', 'None'):
self.visit_NameConstant(node)
return
addSignBit = False
isMixedExpr = (not node.signed) and (self.context == _context.SIGNED)
if n in self.tree.vardict:
addSignBit = isMixedExpr
s = n
elif n in self.tree.argnames:
assert n in self.tree.symdict
addSignBit = isMixedExpr
s = n
elif n in self.tree.symdict:
obj = self.tree.symdict[n]
if isinstance(obj, bool):
s = "1'b%s" % int(obj)
elif isinstance(obj, integer_types):
s = self.IntRepr(obj)
elif isinstance(obj, _Signal):
addSignBit = isMixedExpr
s = str(obj)
elif _isMem(obj):
m = _getMemInfo(obj)
assert m.name
s = m.name
elif isinstance(obj, EnumItemType):
s = obj._toVerilog()
elif (type(obj) in class_types) and issubclass(obj, Exception):
s = n
else:
self.raiseError(node, _error.UnsupportedType,
"%s, %s" % (n, type(obj)))
else:
raise AssertionError("name ref: %s" % n)
if addSignBit:
self.write("$signed({1'b0, ")
self.write(s)
if addSignBit:
self.write("})")
def getName(self, node):
n = node.id
if PY2 and n in ('True', 'False', 'None'):
self.visit_NameConstant(node)
return
addSignBit = False
isMixedExpr = (not node.signed) and (self.context == _context.SIGNED)
if n in self.tree.vardict:
addSignBit = isMixedExpr
s = n
elif n in self.tree.argnames:
assert n in self.tree.symdict
addSignBit = isMixedExpr
s = n
elif n in self.tree.symdict:
obj = self.tree.symdict[n]
if isinstance(obj, bool):
s = "1'b%s" % int(obj)
elif isinstance(obj, integer_types):
s = self.IntRepr(obj)
elif isinstance(obj, _Signal):
addSignBit = isMixedExpr
s = str(obj)
elif _isMem(obj):
m = _getMemInfo(obj)
assert m.name
s = m.name
elif isinstance(obj, EnumItemType):
s = obj._toVerilog()
elif (type(obj) in class_types) and issubclass(obj, Exception):
s = n
else:
self.raiseError(node, _error.UnsupportedType, "%s, %s" % (n, type(obj)))
else:
raise AssertionError("name ref: %s" % n)
if addSignBit:
self.write("$signed({1'b0, ")
self.write(s)
if addSignBit:
self.write("})")
def getName(self, node):
n = node.id
node.obj = None
if n not in self.refStack:
if (n in self.tree.vardict) and (n not in self.tree.nonlocaldict):
self.raiseError(node, _error.UnboundLocal, n)
self.globalRefs.add(n)
if n in self.tree.sigdict:
node.obj = sig = self.tree.sigdict[n]
# mark shadow signal as driven only when they are seen somewhere
if isinstance(sig, _ShadowSignal):
sig._driven = 'wire'
# mark tristate signal as driven if its driver is seen somewhere
if isinstance(sig, _TristateDriver):
sig._sig._driven = 'wire'
if not isinstance(sig, _Signal):
# print "not a signal: %s" % n
pass
else:
if sig._type is bool:
node.edge = sig.posedge
if self.access == _access.INPUT:
self.tree.inputs.add(n)
elif self.access == _access.OUTPUT:
self.tree.kind = _kind.TASK
if n in self.tree.outputs:
node.kind = _kind.REG
self.tree.outputs.add(n)
elif self.access == _access.UNKNOWN:
pass
else:
self.raiseError(node, _error.NotSupported, "Augmented signal assignment")
if n in self.tree.vardict:
obj = self.tree.vardict[n]
if self.access == _access.INOUT: # probably dead code
# upgrade bool to int for augmented assignments
if isinstance(obj, bool):
obj = int(-1)
self.tree.vardict[n] = obj
node.obj = obj
elif n in self.tree.symdict:
node.obj = self.tree.symdict[n]
if _isTupleOfInts(node.obj):
node.obj = _Rom(node.obj)
self.tree.hasRom = True
elif _isMem(node.obj):
m = _getMemInfo(node.obj)
if self.access == _access.INPUT:
m._read = True
elif self.access == _access.OUTPUT:
m._driven = 'reg'
self.tree.outmems.add(n)
elif self.access == _access.UNKNOWN:
pass
else:
assert False, "unexpected mem access %s %s" % (n, self.access)
self.tree.hasLos = True
elif isinstance(node.obj, int):
node.value = node.obj
if n in self.tree.nonlocaldict:
# hack: put nonlocal intbv's in the vardict
self.tree.vardict[n] = v = node.obj
elif n in builtins.__dict__:
node.obj = builtins.__dict__[n]
else:
self.raiseError(node, _error.UnboundLocal, n)
def getName(self, node):
n = node.id
node.obj = None
if n not in self.refStack:
if (n in self.tree.vardict) and (n not in self.tree.nonlocaldict):
self.raiseError(node, _error.UnboundLocal, n)
self.globalRefs.add(n)
if n in self.tree.sigdict:
node.obj = sig = self.tree.sigdict[n]
# mark shadow signal as driven only when they are seen somewhere
if isinstance(sig, _ShadowSignal):
sig._driven = 'wire'
if not isinstance(sig, _Signal):
# print "not a signal: %s" % n
pass
else:
if sig._type is bool:
node.edge = sig.posedge
ws = getattr(sig._val, 'lenStr', False)
ext = getattr(sig._val, 'external', False)
if ws and ws in self.tree.symdict:
_constDict[ws] = self.tree.symdict[ws]
if ext:
_extConstDict[ws] = self.tree.symdict[ws]
if self.access == _access.INPUT:
self.tree.inputs.add(n)
elif self.access == _access.OUTPUT:
self.tree.kind = _kind.TASK
if n in self.tree.outputs:
node.kind = _kind.REG
self.tree.outputs.add(n)
elif self.access == _access.UNKNOWN:
pass
else:
self.raiseError(node, _error.NotSupported, "Augmented signal assignment")
if n in self.tree.vardict:
obj = self.tree.vardict[n]
if self.access == _access.INOUT: # probably dead code
# upgrade bool to int for augmented assignments
if isinstance(obj, bool):
obj = int(-1)
self.tree.vardict[n] = obj
node.obj = obj
elif n in self.tree.symdict:
node.obj = self.tree.symdict[n]
if _isTupleOfInts(node.obj):
node.obj = _Rom(node.obj)
self.tree.hasRom = True
elif _isMem(node.obj):
m = _getMemInfo(node.obj)
if self.access == _access.INPUT:
m._read = True
elif self.access == _access.OUTPUT:
m._driven = 'reg'
self.tree.outmems.add(n)
elif self.access == _access.UNKNOWN:
pass
else:
assert False, "unexpected mem access %s %s" % (n, self.access)
self.tree.hasLos = True
ws = getattr(m.elObj._val, 'lenStr', False)
ext = getattr(m.elObj._val, 'external', False)
if ws and ws in self.tree.symdict:
_constDict[ws] = self.tree.symdict[ws]
if ext:
_extConstDict[ws] = self.tree.symdict[ws]
elif isinstance(node.obj, int):
node.value = node.obj
# put VHDL compliant integer constants in global dict
if n not in _constDict and abs(node.obj) < 2**31:
_constDict[n] = node.obj
if n in self.tree.nonlocaldict:
# hack: put nonlocal intbv's in the vardict
self.tree.vardict[n] = v = node.obj
# typedef string for nonlocal intbv's
ws = getattr(v, 'lenStr', False)
ext = getattr(v, 'external', False)
if ws and ws in self.tree.symdict:
_constDict[ws] = self.tree.symdict[ws]
if ext:
_extConstDict[ws] = self.tree.symdict[ws]
elif n in __builtin__.__dict__:
node.obj = __builtin__.__dict__[n]
else:
self.raiseError(node, _error.UnboundLocal, n)
def getName(self, node):
n = node.id
node.obj = None
if n not in self.refStack:
if (n in self.tree.vardict) and (n not in self.tree.nonlocaldict):
self.raiseError(node, _error.UnboundLocal, n)
self.globalRefs.add(n)
if n in self.tree.sigdict:
node.obj = sig = self.tree.sigdict[n]
# mark shadow signal as driven only when they are seen somewhere
if isinstance(sig, _ShadowSignal):
sig._driven = 'wire'
if not isinstance(sig, _Signal):
# print "not a signal: %s" % n
pass
else:
if sig._type is bool:
node.edge = sig.posedge
ws = getattr(sig._val, 'lenStr', False)
ext = getattr(sig._val, 'external', False)
if ws and ws in self.tree.symdict:
_constDict[ws] = self.tree.symdict[ws]
if ext:
_extConstDict[ws] = self.tree.symdict[ws]
if self.access == _access.INPUT:
self.tree.inputs.add(n)
elif self.access == _access.OUTPUT:
self.tree.kind = _kind.TASK
if n in self.tree.outputs:
node.kind = _kind.REG
self.tree.outputs.add(n)
elif self.access == _access.UNKNOWN:
pass
else:
self.raiseError(node, _error.NotSupported, "Augmented signal assignment")
if n in self.tree.vardict:
obj = self.tree.vardict[n]
if self.access == _access.INOUT: # probably dead code
# upgrade bool to int for augmented assignments
if isinstance(obj, bool):
obj = int(-1)
self.tree.vardict[n] = obj
node.obj = obj
elif n in self.tree.symdict:
node.obj = self.tree.symdict[n]
if _isTupleOfInts(node.obj):
node.obj = _Rom(node.obj)
self.tree.hasRom = True
elif _isMem(node.obj):
m = _getMemInfo(node.obj)
if self.access == _access.INPUT:
m._read = True
elif self.access == _access.OUTPUT:
m._driven = 'reg'
self.tree.outmems.add(n)
elif self.access == _access.UNKNOWN:
pass
else:
assert False, "unexpected mem access %s %s" % (n, self.access)
self.tree.hasLos = True
ws = getattr(m.elObj._val, 'lenStr', False)
ext = getattr(m.elObj._val, 'external', False)
if ws and ws in self.tree.symdict:
_constDict[ws] = self.tree.symdict[ws]
if ext:
_extConstDict[ws] = self.tree.symdict[ws]
elif isinstance(node.obj, int):
node.value = node.obj
# put VHDL compliant integer constants in global dict
if n not in _constDict and abs(node.obj) < 2**31:
_constDict[n] = node.obj
if n in self.tree.nonlocaldict:
# hack: put nonlocal intbv's in the vardict
self.tree.vardict[n] = v = node.obj
# typedef string for nonlocal intbv's
ws = getattr(v, 'lenStr', False)
ext = getattr(v, 'external', False)
if ws and ws in self.tree.symdict:
_constDict[ws] = self.tree.symdict[ws]
if ext:
_extConstDict[ws] = self.tree.symdict[ws]
elif n in __builtin__.__dict__:
node.obj = __builtin__.__dict__[n]
else:
self.raiseError(node, _error.UnboundLocal, n)
def getName(self, node):
n = node.id
node.obj = None
if n not in self.refStack:
if (n in self.tree.vardict) and (n not in self.tree.nonlocaldict):
self.raiseError(node, _error.UnboundLocal, n)
self.globalRefs.add(n)
if n in self.tree.sigdict:
node.obj = sig = self.tree.sigdict[n]
# mark shadow signal as driven only when they are seen somewhere
if isinstance(sig, _ShadowSignal):
sig._driven = 'wire'
# mark tristate signal as driven if its driver is seen somewhere
if isinstance(sig, _TristateDriver):
sig._sig._driven = 'wire'
if not isinstance(sig, _Signal):
# print "not a signal: %s" % n
pass
else:
if sig._type is bool:
node.edge = sig.posedge
if self.access == _access.INPUT:
self.tree.inputs.add(n)
elif self.access == _access.OUTPUT:
self.tree.kind = _kind.TASK
if n in self.tree.outputs:
node.kind = _kind.REG
self.tree.outputs.add(n)
elif self.access == _access.UNKNOWN:
pass
else:
self.raiseError(node, _error.NotSupported,
"Augmented signal assignment")
if n in self.tree.vardict:
obj = self.tree.vardict[n]
if self.access == _access.INOUT: # probably dead code
# upgrade bool to int for augmented assignments
if isinstance(obj, bool):
obj = int(-1)
self.tree.vardict[n] = obj
node.obj = obj
elif n in self.tree.symdict:
node.obj = self.tree.symdict[n]
if _isTupleOfInts(node.obj):
node.obj = _Rom(node.obj)
self.tree.hasRom = True
elif _isMem(node.obj):
m = _getMemInfo(node.obj)
if self.access == _access.INPUT:
m._read = True
elif self.access == _access.OUTPUT:
m._driven = 'reg'
self.tree.outmems.add(n)
elif self.access == _access.UNKNOWN:
pass
else:
assert False, "unexpected mem access %s %s" % (n,
self.access)
self.tree.hasLos = True
elif isinstance(node.obj, int):
node.value = node.obj
if n in self.tree.nonlocaldict:
# hack: put nonlocal intbv's in the vardict
self.tree.vardict[n] = v = node.obj
elif n in builtins.__dict__:
node.obj = builtins.__dict__[n]
else:
self.raiseError(node, _error.UnboundLocal, n)
