def test_three_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, async=True) x = Signal(intbv(3, min=-5000, max=5000)) y = Signal(intbv(4, min=-200, max=200)) intf = IntfWithConstant2() analyze(m_top_const, clock, reset, x, y, intf)
def testForLoopError1(): try: analyze(LoopBench, ForLoopError1) except ConversionError as e: assert e.kind == _error.Requirement else: assert False
def test_hdlobjobj(): clk = Signal(False) srst = Signal(False) x = Signal(intbv(0, min=0, max=16)) y = Signal(intbv(0, min=0, max=16)) hdlobj_inst = HdlObjObj() analyze(hdlobj_inst.method_func, clk, srst, x, y)
def test_hdlobjattrsimple(): clk = Signal(False) srst = Signal(False) x = Signal(intbv(0, min=0, max=16)) y = Signal(intbv(0, min=0, max=16)) hdlobj_inst = HdlObjAttrSimple() analyze(hdlobj_inst.method_func, clk, x, srst, y)
def test_two_analyze(): x,y,z = [Signal(intbv(0, min=-8, max=8)) for _ in range(3)] # fool name check in convertor # to be reviewed x._name = 'x' y._name = 'y' z._name = 'z' analyze(m_top_multi_comb(x, y, z))
def Array8Sorter_v(a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7): toVerilog(Array8Sorter, a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7) analyze(Array8Sorter, a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7) cmd = "cver -q +loadvpi=../../../cosimulation/cver/myhdl_vpi:vpi_compat_bootstrap " + \ "Array8Sorter.v tb_Array8Sorter.v" return Cosimulation(cmd, **locals())
def test_hdlobjnotself(): clk = Signal(False) srst = Signal(False) x = Signal(intbv(0, min=0, max=16)) y = Signal(intbv(0, min=0, max=16)) hdlobj_inst = HdlObjNotSelf() try: analyze(hdlobj_inst.method_func, clk, x, srst, y) except ConversionError, e: assert e.kind == _error.NotSupported
def Array8Sorter_v(a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7): analyze.simulator = 'iverilog' toVerilog(Array8Sorter(a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7)) analyze(Array8Sorter(a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7)) # cmd = "cver -q +loadvpi=../../../cosimulation/cver/myhdl_vpi:vpi_compat_bootstrap " + \ # "Array8Sorter.v tb_Array8Sorter.v" subprocess.call("iverilog -o Array8Sorter.o Array8Sorter.v tb_Array8Sorter.v", shell=True) cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi Array8Sorter.o" return Cosimulation(cmd, **locals())
def test_one_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=1, isasync=False) sdi = Signal(bool(0)) sdo = Signal(bool(0)) nested = Signal(bool(0)) assert analyze(interfaces_top(clock, reset, sdi, sdo, nested)) == 0
def test_issue_13(): reset = ResetSignal(0, active=1, async=False) clk = Signal(bool(0)) d = Signal(intbv(0)[32:]) en = Signal(bool(0)) q = Signal(intbv(0)[8:]) # toVHDL.numeric_ports = False assert analyze(issue_13, reset, clk, d, en, q) == 0
def testForLoopError1(): try: analyze(LoopBench, ForLoopError1) except ConversionError, e: assert e.kind == _error.Requirement
def convert(): q, d, clk = [Signal(bool(0)) for i in range(3)] toVerilog(dff, q, d, clk) analyze(dff, q, d, clk)
def test_two_level_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0,active=0,async=True) ia = MyIntf() ib = MyIntf() analyze(m_two_level(clock,reset,ia,ib))
def convert(): q, d, g = [Signal(bool(0)) for i in range(3)] toVerilog(latch, q, d, g) conversion.analyze(latch, q, d, g)
def testForLoopError2(): try: analyze(LoopBench, ForLoopError2) except ConversionError, e: assert e.kind == _error.Requirement
def test_one_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=False) sdi = Signal(bool(0)) sdo = Signal(bool(0)) analyze(m_top, clock, reset, sdi, sdo)
def test_two_analyze(): x, y, z = [Signal(intbv(0, min=-8, max=8)) for _ in range(3)] analyze(m_top_multi_comb, x, y, z)
def test_two_analyze(): x,y,z = [Signal(intbv(0, min=-8, max=8)) for _ in range(3)] analyze(m_top_multi_comb, x, y, z)
def test_one_analyze(): x,y,z = [Signal(intbv(0, min=-8, max=8)) for _ in range(3)] analyze(m_top_assign, x, y, z)
def test_issue_117_3(): clk, sdi = [Signal(bool(0)) for _ in range(2)] pdo = Signal(intbv(0)[8:]) sel = Signal(intbv(0, min=0, max=3)) toVHDL.name = toVerilog.name = 'issue_117_3' assert analyze(issue_117, clk, sdi, pdo, sel, const=intbv(0)[1:])== 0
def test_issue_134(): """ check for port name collision""" assert analyze(issue_134, AB(), AB()) == 0
def test_issue_18(): toVHDL.std_logic_ports = True assert analyze(issue_18, dout, din, addr, we, clk) == 0
def test_bug_3577799(): assert analyze(bug_3577799, clk, reset_clk, wr_data, wr, rd_data) == 0
def testForLoopError2(): with pytest.raises(ConversionError) as e: analyze(test_loop(ForLoopError2)) assert e.value.kind == _error.Requirement
def test_issue_98_3(): sda_i, sda_o, scl_i, scl_o = [Signal(intbv(0)[1:0]) for i in range(4)] sda, scl = [TristateSignal(intbv(0)[1:0]) for i in range(2)] toVHDL.name = toVerilog.name = 'issue_98_3' assert analyze(issue_98, sda, scl, sda_i, sda_o, scl_i, scl_o) == 0
def test_one_analyze(): x, y, z = [Signal(intbv(0, min=-8, max=8)) for _ in range(3)] analyze(m_top_assign, x, y, z)
def test_name_conflicts_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, async=False) a,b,c = (Intf(),Intf(),Intf(),) analyze(m_test_intf(clock,reset,a,b,c))
def test_issue_98_1(): sda_i, sda_o, scl_i, scl_o = [Signal(False) for i in range(4)] sda, scl = [TristateSignal(False) for i in range(2)] toVHDL.name = toVerilog.name = 'issue_98_1' assert analyze(issue_98, sda, scl, sda_i, sda_o, scl_i, scl_o) == 0