def _writeModuleHeader(f, intf, doc):
print("module %s (" % intf.name, file=f)
b = StringIO()
for portname in intf.argnames:
print(" %s," % portname, file=b)
print(b.getvalue()[:-2], file=f)
b.close()
print(");", file=f)
print(doc, file=f)
print(file=f)
for portname in intf.argnames:
s = intf.argdict[portname]
if s._name is None:
raise ToVerilogError(_error.ShadowingSignal, portname)
if s._inList:
raise ToVerilogError(_error.PortInList, portname)
# make sure signal name is equal to its port name
s._name = portname
r = _getRangeString(s)
p = _getSignString(s)
if s._driven:
if s._read:
warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
category=ToVerilogWarning)
print("output %s%s%s;" % (p, r, portname), file=f)
if s._driven == 'reg':
print("reg %s%s%s;" % (p, r, portname), file=f)
else:
print("wire %s%s%s;" % (p, r, portname), file=f)
else:
if not s._read:
warnings.warn("%s: %s" % (_error.UnusedPort, portname),
category=ToVerilogWarning)
print("input %s%s%s;" % (p, r, portname), file=f)
print(file=f)
def __call__(self, func, *args, **kwargs):
global _converting
if _converting:
return func(*args, **kwargs) # skip
else:
# clean start
sys.setprofile(None)
from myhdl import _traceSignals
if _traceSignals._tracing:
raise ToVerilogError("Cannot use toVerilog while tracing signals")
if not callable(func):
raise ToVerilogError(_error.FirstArgType, "got %s" % type(func))
_converting = 1
if self.name is None:
name = func.func_name
else:
name = str(self.name)
try:
h = _HierExtr(name, func, *args, **kwargs)
finally:
_converting = 0
vpath = name + ".v"
vfile = open(vpath, 'w')
### initialize properly ###
_genUniqueSuffix.reset()
siglist, memlist = _analyzeSigs(h.hierarchy)
arglist = _flatten(h.top)
# print h.top
_checkArgs(arglist)
genlist = _analyzeGens(arglist, h.absnames)
_annotateTypes(genlist)
intf = _analyzeTopFunc(func, *args, **kwargs)
intf.name = name
doc = _makeDoc(inspect.getdoc(func))
self._convert_filter(h, intf, siglist, memlist, genlist)
_writeFileHeader(vfile, vpath, self.timescale)
_writeModuleHeader(vfile, intf, doc)
_writeSigDecls(vfile, intf, siglist, memlist)
_convertGens(genlist, vfile)
_writeModuleFooter(vfile)
vfile.close()
# don't write testbench if module has no ports
if len(intf.argnames) > 0 and not toVerilog.no_testbench:
tbpath = "tb_" + vpath
tbfile = open(tbpath, 'w')
_writeTestBench(tbfile, intf)
tbfile.close()
### clean-up properly ###
self._cleanup(siglist)
return h.top
def _writeSigDecls(f, intf, siglist, memlist):
constwires = []
for s in siglist:
if not s._used:
continue
if s._name in intf.argnames:
continue
r = _getRangeString(s)
p = _getSignString(s)
if s._driven:
if not s._read:
warnings.warn("%s: %s" % (_error.UnreadSignal, s._name),
category=ToVerilogWarning)
k = 'wire'
if s._driven == 'reg':
k = 'reg'
# the following line implements initial value assignments
# print >> f, "%s %s%s = %s;" % (k, r, s._name, int(s._val))
print("%s %s%s%s;" % (k, p, r, s._name), file=f)
elif s._read:
# the original exception
# raise ToVerilogError(_error.UndrivenSignal, s._name)
# changed to a warning and a continuous assignment to a wire
warnings.warn("%s: %s" % (_error.UndrivenSignal, s._name),
category=ToVerilogWarning)
constwires.append(s)
print("wire %s%s;" % (r, s._name), file=f)
print(file=f)
for m in memlist:
if not m._used:
continue
# infer attributes for the case of named signals in a list
for i, s in enumerate(m.mem):
if not m._driven and s._driven:
m._driven = s._driven
if not m._read and s._read:
m._read = s._read
if not m._driven and not m._read:
continue
r = _getRangeString(m.elObj)
p = _getSignString(m.elObj)
k = 'wire'
if m._driven:
k = m._driven
print("%s %s%s%s [0:%s-1];" % (k, p, r, m.name, m.depth), file=f)
print(file=f)
for s in constwires:
if s._type in (bool, intbv):
c = int(s.val)
else:
raise ToVerilogError("Unexpected type for constant signal",
s._name)
print("assign %s = %s;" % (s._name, c), file=f)
print(file=f)
# shadow signal assignments
for s in siglist:
if hasattr(s, 'toVerilog') and s._driven:
print(s.toVerilog(), file=f)
print(file=f)
def raiseError(self, msg, info):
raise ToVerilogError("Error in user defined Verilog code", msg, info)
def _checkArgs(arglist):
for arg in arglist:
if not isinstance(arg,
(GeneratorType, _Instantiator, _UserVerilogCode)):
raise ToVerilogError(_error.ArgType, arg)
def raiseError(self, node, kind, msg=""):
lineno = self.getLineNo(node)
info = "in file %s, line %s:\n " % \
(self.tree.sourcefile, self.tree.lineoffset + lineno)
raise ToVerilogError(kind, msg, info)
def __call__(self, func, *args, **kwargs):
global _converting
if _converting:
return func(*args, **kwargs) # skip
else:
# clean start
sys.setprofile(None)
from myhdl import _traceSignals
if _traceSignals._tracing:
raise ToVerilogError("Cannot use toVerilog while tracing signals")
if not isinstance(func, _Block):
if not callable(func):
raise ToVerilogError(_error.FirstArgType,
"got %s" % type(func))
_converting = 1
if self.name is None:
name = func.__name__
if isinstance(func, _Block):
name = func.func.__name__
else:
name = str(self.name)
if isinstance(func, _Block):
try:
h = _getHierarchy(name, func)
finally:
_converting = 0
else:
warnings.warn(
"\n toVerilog(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html",
stacklevel=2)
try:
h = _HierExtr(name, func, *args, **kwargs)
finally:
_converting = 0
if self.directory is None:
directory = ''
else:
directory = self.directory
vfilename = name + ".v"
vpath = os.path.join(directory, vfilename)
vfile = open(vpath, 'w')
### initialize properly ###
_genUniqueSuffix.reset()
arglist = _flatten(h.top)
# print h.top
_checkArgs(arglist)
genlist = _analyzeGens(arglist, h.absnames)
siglist, memlist = _analyzeSigs(h.hierarchy)
_annotateTypes(genlist)
# infer interface
if isinstance(func, _Block):
# infer interface after signals have been analyzed
func._inferInterface()
intf = func
else:
intf = _analyzeTopFunc(func, *args, **kwargs)
intf.name = name
doc = _makeDoc(inspect.getdoc(func))
self._convert_filter(h, intf, siglist, memlist, genlist)
_writeFileHeader(vfile, vpath, self.timescale)
_writeModuleHeader(vfile, intf, doc)
_writeSigDecls(vfile, intf, siglist, memlist)
_convertGens(genlist, vfile)
_writeModuleFooter(vfile)
vfile.close()
# don't write testbench if module has no ports
if len(intf.argnames) > 0 and not toVerilog.no_testbench:
tbpath = os.path.join(directory, "tb_" + vfilename)
tbfile = open(tbpath, 'w')
_writeTestBench(tbfile, intf, self.trace)
tbfile.close()
# build portmap for cosimulation
portmap = {}
for n, s in intf.argdict.items():
if hasattr(s, 'driver'):
portmap[n] = s.driver()
else:
portmap[n] = s
self.portmap = portmap
### clean-up properly ###
self._cleanup(siglist)
return h.top