def compare_ref_with_res_files(self):
'''|
| Check the results from files
|________'''
for name, (ref,res) in self.ref_data.items():
try:
with open(ref[0]["file"], "rb") as expfile, open(res[0]["file"], "rb") as resfile:
linesref = expfile.readlines()
linesres = resfile.readlines()
assert(len(linesref)==len(linesres)), "\tCOMPARE ERROR: Length mismatch for \"{:}\". Detected lengths: \n\t len(expected)={:} \n\t len(detected)={:} \n\t".format(name, len(linesref), len(linesres))
k=1
for lineref, lineres in zip(linesref, linesres):
assert (lineref.strip()==lineres.strip()), "\tCOMPARE ERROR: \"{:}\" payload #{:}: Payload does not match: \n\t expected={:} \n\t detected={:}".format(name, k, lineref.strip(), lineres.strip())
except IOError:
mylog.err("Compare reference with result files: File not found")
def impl2string(self, conf):
'''|
| Converts a dictionary (containing implementation information) into a string
|________'''
impl = [self.BEH, self.RTL, self.VRG]
impl_str = ['BEHAVIOR', 'MyHDL_RTL', '(external) VERILOG']
s = ''
for key,value in conf.iteritems():
if len(conf) == 1:
return impl_str[value]
if value not in impl:
mylog.err(key + ": Wrong implementation model selected: (" + str(value) + ")! Exit...")
exit()
s += key + " = " + impl_str[value] + ", "
return s[:-2]
def convert(self, hdl='verilog', params={}, verbose=True):
'''|
| Converts convertible to HDL
|________'''
if self.IMPL == self.BEH:
mylog.err("Behavior models can not be converted to verilog!")
exit(0)
self.is_top = True
# Add resets, clock and overwritten parameters to top interface
top_kwargs = {}
top_kwargs.update(self.get_all_clocks())
top_kwargs.update(self.get_all_resets())
top_kwargs.update(self.get_all_parameters(params, verbose))
str_params = ''
for parameter, value in self.get_all_parameters(params, verbose).iteritems():
str_params += parameter + ' = ' + str(value) + ', '
if verbose and str_params != '':
mylog.infob('Parameters: {}'.format(str_params[:-2]))
# Add flatten interface signals to top interface
for x in self.get_all_interfaces().itervalues():
top_kwargs.update(x.get_all_signals())
if verbose:
mylog.infob('Converting to {}...'.format(hdl))
if hdl.lower()=='verilog':
toVerilog.name = self.get_name() + self.top_suffix
toVerilog(self.top, **top_kwargs)
elif hdl.lower()=='vhdl':
toVHDL.name = self.get_name() + self.top_suffix
toVHDL(self.top, **top_kwargs)
else:
raise ValueError("Unknown HDL: {}".format(hdl))
