class Peripherals(Elaboratable):
def __init__(self, rom_file: str):
super().__init__()
self.rom_file = rom_file
self.segments = Signal(8)
self.anodes = Signal(8)
self.ibus = Record(wishbone.wishbone_layout)
self.dbus = Record(wishbone.wishbone_layout)
def elaborate(self, _: Optional[Platform]) -> Module:
m = Module()
# Set up ROM/RAM peripherals
m.submodules.rom = rom = XilinxDualPortBRAM(read_only=True,
init_file=self.rom_file)
m.submodules.ram = ram = XilinxDualPortBRAM()
# Set up the display peripheral
bank = seven_segment.DisplayBank()
m.d.comb += self.segments.eq(bank.segments)
m.d.comb += self.anodes.eq(bank.anodes)
m.submodules.sseg = sseg = SevenSegmentDisplay(bank)
# Connect peripherals to the instruction and data buses
m.d.comb += self.ibus.connect(rom.abus)
m.submodules.dmux = dmux = WishboneMux((
('rom', 0x00000000, 4 * 1024, rom.bbus),
('ram', 0x00001000, 4 * 1024, ram.abus),
('sseg', 0x00002000, 0x100, sseg.wbus),
))
m.d.comb += self.dbus.connect(dmux.wbus)
return m
class SevenSegmentDisplay(Elaboratable):
def __init__(self, output: seven_segment.DisplayBank):
super().__init__()
self.output = output
self.wbus = Record(wishbone.wishbone_layout)
def elaborate(self, _: Optional[Platform]) -> Module:
m = Module()
m.submodules.regs = regs = WishboneRegisters(size=0x100,
regs=[('data', 0x00, 4,
0x0000_0000)])
m.d.comb += self.wbus.connect(regs.wbus)
m.submodules.digit = digit = seven_segment.HexDigitLUT()
digits = Array(regs.data[4 * i:4 * (i + 1)] for i in range(8))
m.submodules.mux = mux = seven_segment.DisplayMultiplexer(self.output)
m.d.comb += digit.input.eq(digits[mux.select])
m.d.comb += mux.segments.eq(digit.output)
m.d.comb += mux.duty_cycle.eq(-1)
return m
