def __init__(self, **kwargs): super().__init__() self._cpu = Minerva(**kwargs) self.ibus = wishbone.Interface(addr_width=30, data_width=32, granularity=8, features={"err", "cti", "bte"}) self.dbus = wishbone.Interface(addr_width=30, data_width=32, granularity=8, features={"err", "cti", "bte"}) self.ip = Signal.like(self._cpu.external_interrupt)
def __init__(self, *args, **kwargs): # Create the basic Minerva processor... super().__init__(*args, **kwargs) # ... and replace its Record-based busses with nMigen-soc ones. self.ibus = wishbone.Interface(addr_width=30, data_width=32, features=self.MINERVA_BUS_FEATURES) self.dbus = wishbone.Interface(addr_width=30, data_width=32, features=self.MINERVA_BUS_FEATURES)
def window(self, *, addr_width, data_width, granularity=None, features=frozenset(), alignment=0, addr=None, sparse=None): """Request a window to a subordinate bus. See :meth:`nmigen_soc.wishbone.Decoder.add` for details. Return value ------------ An instance of :class:`nmigen_soc.wishbone.Interface`. """ window = wishbone.Interface(addr_width=addr_width, data_width=data_width, granularity=granularity, features=features) granularity_bits = log2_int(data_width // window.granularity) window.memory_map = MemoryMap(addr_width=addr_width + granularity_bits, data_width=window.granularity, alignment=alignment) self._windows.append((window, addr, sparse)) return window
def __init__(self, *, size, data_width=32, granularity=8, writable=True): super().__init__() if not isinstance(size, int) or size <= 0 or size & size - 1: raise ValueError( "Size must be an integer power of two, not {!r}".format(size)) if size < data_width // granularity: raise ValueError( "Size {} cannot be lesser than the data width/granularity ratio " "of {} ({} / {})".format(size, data_width // granularity, data_width, granularity)) self._mem = Memory(depth=(size * granularity) // data_width, width=data_width, name=self.name) self.bus = wishbone.Interface(addr_width=log2_int(self._mem.depth), data_width=self._mem.width, granularity=granularity, features={"cti", "bte"}) map = MemoryMap(addr_width=log2_int(size), data_width=granularity) map.add_resource(self._mem, size=size) self.bus.memory_map = map self.size = size self.granularity = granularity self.writable = writable
def __init__(self, divisor): self.divisor = divisor # # I/O port # self.tx = Signal() self.bus = wishbone.Interface(addr_width=0, data_width=8) self.bus.memory_map = memory.MemoryMap(addr_width=1, data_width=8)
def __init__(self, divisor, pins, bus=None): if bus is not None: self.bus = bus else: self.bus = wishbone.Interface(addr_width=30, data_width=32, granularity=8) self._pins = pins self._divisor = divisor
def __init__(self, *, addr_width, data_width=32, granularity=8, init=None, read_only=False, byteorder="little", name="ram"): """ Parameters: addr_width -- The -bus- address width for the relevant memory. Determines the size of the memory. data_width -- The width of each memory word. granularity -- The number of bits of data per each address. init -- Optional. The initial value of the relevant memory. Should be an array of integers, a filename, or a bytes-like object. If bytes are provided, the byteorder parametera allows control over their interpretation. If a filename is provided, this filename will not be read until elaboration; this allows reading the file to be deferred until the very last minute in e.g. systems that generate the relevant file during build. read_only -- If true, this will ignore writes to this memory, so it effectively acts as a ROM fixed to its initialization value. byteorder -- Sets the byte order of the initializer value. Ignored unless a bytes-type initializer is provided. name -- A descriptive name for the given memory. """ self.name = name self.read_only = read_only self.data_width = data_width self.initial_value = init self.byteorder = byteorder # Our granularity determines how many bits of data exist per single address. # Often, this isn't the same as our data width; which means we'll wind up with # two different address widths: a 'local' one where each address corresponds to a # data value in memory; and a 'bus' one where each address corresponds to a granularity- # sized chunk of memory. self.granularity = granularity self.bus_addr_width = addr_width # Our bus addresses are more granular than our local addresses. # Figure out how many more bits exist in our bus addresses, and use # that to figure out our local bus size. self.bytes_per_word = data_width // granularity self.bits_in_bus_only = int(math.log2(self.bytes_per_word)) self.local_addr_width = self.bus_addr_width - self.bits_in_bus_only # Create our wishbone interface. # Note that we provide the -local- address to the Interface object; as it automatically factors # in our extra bits as it computes our granularity. self.bus = wishbone.Interface(addr_width=self.local_addr_width, data_width=data_width, granularity=granularity) self.bus.memory_map = memory.MemoryMap(addr_width=self.bus_addr_width, data_width=granularity) self.bus.memory_map.add_resource(self, size=2**addr_width)
def __init__(self, *, clk_freq, dramcore_addr, ddr_addr): self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8, features={"cti", "bte"}) self.bus = wishbone.Interface(addr_width=30, data_width=32, granularity=8) tck = 2 / (2 * 2 * 100e6) nphases = 2 databits = 16 nranks = 1 addressbits = 14 bankbits = 3 cl, cwl = get_cl_cw("DDR3", tck) cl_sys_latency = get_sys_latency(nphases, cl) cwl_sys_latency = get_sys_latency(nphases, cwl) rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl) wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl) physettings = PhySettings(phytype="ECP5DDRPHY", memtype="DDR3", databits=databits, dfi_databits=4 * databits, nranks=nranks, nphases=nphases, rdphase=rdphase, wrphase=wrphase, rdcmdphase=rdcmdphase, wrcmdphase=wrcmdphase, cl=cl, cwl=cwl, read_latency=2 + cl_sys_latency + 2 + log2_int(4 // nphases) + 4, write_latency=cwl_sys_latency) ddrmodule = MT41K256M16(clk_freq, "1:2") self.ddrphy = FakePHY(module=ddrmodule, settings=physettings, verbosity=SDRAM_VERBOSE_DBG) self.dramcore = gramCore(phy=self.ddrphy, geom_settings=ddrmodule.geom_settings, timing_settings=ddrmodule.timing_settings, clk_freq=clk_freq) self._decoder.add(self.dramcore.bus, addr=dramcore_addr) self.drambone = gramWishbone(self.dramcore) self._decoder.add(self.drambone.bus, addr=ddr_addr) self.memory_map = self._decoder.bus.memory_map self.clk_freq = clk_freq
def __init__(self, divisor): """ Parameters: divisor -- number of `sync` clock cycles per bit period """ self.divisor = divisor # # I/O port # self.tx = Signal() self.bus = wishbone.Interface(addr_width=0, data_width=8) self.bus.memory_map = memory.MemoryMap(addr_width=1, data_width=8)
def __init__(self, core, data_width=32, granularity=8): super().__init__(name="wishbone") self.native_port = core.crossbar.get_native_port() self.ratio = self.native_port.data_width // data_width addr_width = log2_int(core.size // (self.native_port.data_width // data_width)) self.bus = wishbone.Interface(addr_width=addr_width + log2_int(self.ratio), data_width=data_width, granularity=granularity) map = MemoryMap(addr_width=addr_width + log2_int(self.ratio) + log2_int(data_width // granularity), data_width=granularity) self.bus.memory_map = map
def test_simple(self): wb = wishbone.Interface(addr_width=30, data_width=32, granularity=8, features=["err", "rty", "cti", "bte", "lock"]) wb_fc = Signal(3) wb_ipl = Signal(3) dut = WishboneTo68000(wb, wb_fc, wb_ipl) def sim_test(): # test byte reads for b in range(0, 4): yield wb.adr.eq(0x0) yield wb.cyc.eq(1) yield wb.stb.eq(1) yield wb.sel.eq(1 << b) yield wb.we.eq(0) while ((yield dut.lds_) & (yield dut.uds_)) != 0: yield Tick() yield Delay(1e-9) if b > 1: self.assertEqual((yield dut.addr), 0x0) else: self.assertEqual((yield dut.addr), 0x1) self.assertEqual((yield dut.as_), 0) yield dut.i_data.eq((yield dut.addr)) yield dut.dtack_.eq(0) yield Tick() yield Delay(1e-9) while (yield wb.ack) == 0: yield Tick() yield Delay(1e-9) yield wb.cyc.eq(0) yield wb.stb.eq(0) self.assertEqual((yield dut.as_), 1) self.assertEqual((yield dut.lds_), 1) self.assertEqual((yield dut.uds_), 1) yield Tick() # test word reads yield wb.adr.eq(0xaaa) yield wb.cyc.eq(1) yield wb.stb.eq(1) yield wb.sel.eq(0xf) yield wb.we.eq(0) while ((yield dut.lds_) & (yield dut.uds_)) != 0: yield Tick() yield Delay(1e-9) self.assertEqual((yield dut.addr), 0xaaa << 1) self.assertEqual((yield dut.as_), 0) yield dut.i_data.eq((yield dut.addr)) yield dut.dtack_.eq(0) yield Tick() yield Delay(1e-9) yield wb.cyc.eq(0) yield wb.stb.eq(0) self.assertEqual((yield dut.as_), 1) self.assertEqual((yield dut.lds_), 1) self.assertEqual((yield dut.uds_), 1) while ((yield dut.lds_) & (yield dut.uds_)) != 0: yield Tick() yield Delay(1e-9) yield dut.i_data.eq((yield dut.addr)) while (yield wb.ack) == 0: yield Tick() yield Delay(1e-9) yield Tick() # test interrupt yield wb.adr.eq(0xfffffff9) # 32 bit level lower 3 bits yield wb_ipl.eq(1) yield wb_fc.eq(0x7) yield wb.cyc.eq(1) yield wb.stb.eq(1) yield wb.sel.eq(0xf) yield wb.we.eq(0) while ((yield dut.lds_) & (yield dut.uds_)) != 0: yield Tick() yield Delay(1e-9) self.assertEqual((yield dut.addr), ((0xfffffff9 << 1) + 1) & 0x7fffff) self.assertEqual((yield dut.as_), 0) yield dut.i_data.eq((yield dut.addr)) yield dut.dtack_.eq(0) yield Tick() yield Delay(1e-9) yield wb.cyc.eq(0) yield wb.stb.eq(0) self.assertEqual((yield dut.as_), 1) self.assertEqual((yield dut.lds_), 1) self.assertEqual((yield dut.uds_), 1) yield Tick() sim = Simulator(dut) sim.add_clock(1e-6) sim.add_sync_process(sim_test) with sim.write_vcd(vcd_file=open("wb_to_68k.vcd", "w")): sim.run()
def __init__(self, divisor, pins): self.bus = wishbone.Interface(addr_width=30, data_width=32, granularity=8) self._pins = pins self._divisor = divisor
def __init__(self): self.bus = wishbone.Interface(addr_width=17, data_width=8) self.bus.memory_map = MemoryMap(addr_width=17, data_width=8) f = open('../x68kd11s/iplromxv.dat', 'rb') dat = f.read() self.mem = Memory(width=8, depth=131072, init=dat)