def initialize_slave_lists(self):
bus_type = self.controller.get_bus()
paths = utils.get_local_verilog_paths()
slave_list = utils.get_slave_list(bus_type, paths)
peripheral_dict = {}
memory_dict = {}
for slave in slave_list:
tags = vutils.get_module_tags( filename = slave,
keywords=["SDB_ABI_VERSION_MAJOR", "SDB_NAME"],
bus = self.controller.get_bus(),
user_paths = paths)
#print "Tags: %s" % str(tags)
#core_id = int(tags["keywords"]["SDB_NAME"])
device_abi_major = int(tags["keywords"]["SDB_ABI_VERSION_MAJOR"], 0)
memory_abi_major = device_manager.get_device_id_from_name("memory")
if device_abi_major == memory_abi_major:
memory_dict[tags["module"]] = tags
else:
peripheral_dict[tags["module"]] = tags
self.project_actions.setup_peripheral_bus_list.emit(peripheral_dict)
self.project_actions.setup_memory_bus_list.emit(memory_dict)
#self.project_view.get_designer_scene().view.fit_in_view()
self.project_actions.update_project_name.connect(self.actions.update_project_name)
self.project_actions.add_constraint_file.connect(self.add_constraint)
self.project_actions.remove_constraint_file.connect(self.remove_constraint)
self.project_actions.add_default_board_constraint.connect(self.add_default_board_constraint)
self.project_actions.remove_default_board_constraint.connect(self.remove_default_board_constraint)
self.project_actions.commit_slave_parameters.connect(self.commit_slave_parameters)
self.project_actions.commit_slave_integration_list.connect(self.commit_slave_integration_list)
def test_get_module_tags(self):
tags = vutils.get_module_tags(TEST_MODULE_LOCATION)
#print "tags: %s" % str(tags)
assert "parameters" in tags
assert "keywords" in tags
assert "arbiter_masters" in tags
assert "module" in tags
assert tags["module"] == "wb_test"
assert "ports" in tags
def test_get_module_tags(self):
tags = vutils.get_module_tags(TEST_MODULE_LOCATION)
#print "tags: %s" % str(tags)
assert "parameters" in tags
assert "keywords" in tags
assert "arbiter_masters" in tags
assert "module" in tags
assert tags["module"] == "wb_test"
assert "ports" in tags
def setup_host_interface(self):
#Host interface is always present, if there is a user configuration
#Associated with it, set all the appropriate values
#print "setup host interface: %s" % (self.config_dict["PROJECT_NAME"])
if "INTERFACE" not in self.config_dict:
print "Interface is not in project tags"
return
project_tags = self.config_dict["INTERFACE"]
self.set_node_project_tags(HOST_INTERFACE, project_tags)
module_tags = {}
if "filename" in project_tags:
filename = project_tags["filename"]
try:
filepath = utils.find_rtl_file_location(filename, self.paths)
module_tags = vutils.get_module_tags(filepath)
except:
print "%s: Could not find Host Interface for file: %s" % (__file__, filename)
self.set_node_module_tags(HOST_INTERFACE, module_tags)
self.update_node_ports(HOST_INTERFACE)
if "bind" in project_tags:
self.set_node_bindings(HOST_INTERFACE, cu.expand_user_constraints(project_tags["bind"]))
def generate_wb_mem_interconnect(tags = {}, user_paths = [], debug = False):
if "MEMORY" not in tags:
return ""
num_slaves = len(tags["MEMORY"].keys())
if debug: print "Number of slaves: %d" % num_slaves
buf = ""
#Allow errors to pass up to the calling class
directory = utils.get_local_verilog_path("nysa-verilog")
wb_i_loc = os.path.join( directory,
"verilog",
"wishbone",
"interconnect",
"wishbone_mem_interconnect.v")
f = open(wb_i_loc, "r")
buf = f.read()
f.close()
template = Template(buf)
port_buf = ""
port_def_buf = ""
mem_select_buf = ""
assign_buf = ""
data_block_buf = ""
ack_block_buf = ""
int_block_buf = ""
param_buf = ""
#start with 1 to account for SDB
num_mems = 0
if (tags.has_key("MEMORY")):
#got a list of all the slaves to add to make room for
mem_list = tags["MEMORY"]
num_mems = num_mems + len(mem_list)
if num_mems == 0:
return ""
if debug:
"Memory Keys\n\n"
for key in tags["MEMORY"]:
print key + ":" + str(tags["MEMORY"][key])
print "\n\n"
slave_keywords = [
"SDB_ABI_VERSION_MAJOR",
"SDB_ABI_VERSION_MINOR",
"SDB_SIZE"
]
mem_offset = 0
#generate the parameters
for i in range(0, num_mems):
key = tags["MEMORY"].keys()[i]
absfilename = utils.find_rtl_file_location(tags["MEMORY"][key]["filename"], user_paths)
#print "filename: %s" % absfilename
slave_tags = vutils.get_module_tags(filename = absfilename,
bus = "wishbone",
keywords = slave_keywords,
project_tags = tags)
if debug:
print "slave tags: " + str(slave_tags)
mem_size = int(slave_tags["keywords"]["SDB_SIZE"].strip(), 0)
param_buf = param_buf + "parameter MEM_SEL_%d\t=\t%d;\n" % (i, i)
#param_buf = param_buf + "parameter MEM_OFFSET_%d\t=\t %d;\n" % (i, mem_offset)
param_buf = param_buf + "parameter MEM_OFFSET_%d\t=\t 32'h%08X;\n" % (i, mem_offset)
param_buf = param_buf + "parameter MEM_SIZE_%d\t=\t 32'h%02X;\n" % (i, mem_size)
mem_offset += mem_size
#generate the memory select logic
mem_select_buf = "reg [31:0] mem_select;\n"
mem_select_buf += "\n"
mem_select_buf += "always @(rst or i_m_adr or mem_select) begin\n"
mem_select_buf += "\tif (rst) begin\n"
mem_select_buf += "\t\t//nothing selected\n"
mem_select_buf += "\t\tmem_select <= 32'hFFFFFFFF;\n"
mem_select_buf += "\tend\n"
mem_select_buf += "\telse begin\n"
for i in range (num_mems):
if (i == 0):
mem_select_buf += "\t\tif "
else:
mem_select_buf += "\t\telse if "
mem_select_buf += "((i_m_adr >= MEM_OFFSET_%d) && (i_m_adr < (MEM_OFFSET_%d + MEM_SIZE_%d))) begin\n" % (i, i, i)
mem_select_buf += "\t\t\tmem_select <= MEM_SEL_%d;\n" % i
mem_select_buf += "\t\tend\n"
mem_select_buf += "\t\telse begin\n"
mem_select_buf += "\t\t\tmem_select <= 32'hFFFFFFFF;\n"
mem_select_buf += "\t\tend\n"
mem_select_buf += "\tend\n"
mem_select_buf += "end\n"
#Ports
for i in range (0, num_slaves):
port_buf += "\t//Slave %d\n" % i
port_buf += "\toutput\t\t\t\t\t\t\to_s%d_we,\n" % i
port_buf += "\toutput\t\t\t\t\t\t\to_s%d_cyc,\n" % i
port_buf += "\toutput\t\t\t\t\t\t\to_s%d_stb,\n" % i
port_buf += "\toutput\t\t[3:0]\t\t\to_s%d_sel,\n" % i
port_buf += "\tinput\t\t\t\t\t\t\t\ti_s%d_ack,\n" % i
port_buf += "\toutput\t\t[31:0]\t\to_s%d_dat,\n" % i
port_buf += "\tinput\t\t\t[31:0]\t\ti_s%d_dat,\n" % i
port_buf += "\toutput\t\t[31:0]\t\to_s%d_adr,\n" % i
port_buf += "\tinput\t\t\t\t\t\t\t\ti_s%d_int" % i
#if this isn't the last slave add a comma
if (i < num_slaves - 1):
port_buf += ",\n"
port_buf += "\n"
#assign defines
for i in range (0, num_mems):
assign_buf += "assign o_s%d_we =\t(mem_select == MEM_SEL_%d) ? i_m_we: 1'b0;\n" % (i, i)
assign_buf += "assign o_s%d_stb =\t(mem_select == MEM_SEL_%d) ? i_m_stb: 1'b0;\n" % (i, i)
assign_buf += "assign o_s%d_sel =\t(mem_select == MEM_SEL_%d) ? i_m_sel: 4'b0;\n" % (i, i)
assign_buf += "assign o_s%d_cyc =\t(mem_select == MEM_SEL_%d) ? i_m_cyc: 1'b0;\n" % (i, i)
if i == 0:
assign_buf += "assign o_s%d_adr =\t(mem_select == MEM_SEL_%d) ? i_m_adr: 32'h0;\n" % (i, i)
else:
assign_buf += "assign o_s%d_adr =\t(mem_select == MEM_SEL_%d) ? i_m_adr - MEM_OFFSET_%d: 32'h0;\n" %(i, i, i)
assign_buf += "assign o_s%d_dat =\t(mem_select == MEM_SEL_%d) ? i_m_dat: 32'h0;\n" % (i, i)
assign_buf +="\n"
#data in block
data_block_buf = "//data in from slave\n"
data_block_buf += "always @ (mem_select"
for i in range (0, num_mems):
data_block_buf += " or i_s%d_dat" % i
data_block_buf += ") begin\n\tcase (mem_select)\n"
for i in range (0, num_mems):
data_block_buf += "\t\tMEM_SEL_%d: begin\n\t\t\to_m_dat <= i_s%d_dat;\n\t\tend\n" % (i, i)
data_block_buf += "\t\tdefault: begin\n\t\t\to_m_dat <= 32\'h0000;\n\t\tend\n\tendcase\nend\n\n"
#ack in block
ack_block_buf = "//ack in from mem slave\n"
ack_block_buf += "always @ (mem_select"
for i in range (0, num_mems):
ack_block_buf += " or i_s%d_ack" % i
ack_block_buf += ") begin\n\tcase (mem_select)\n"
for i in range (0, num_mems):
ack_block_buf += "\t\tMEM_SEL_%d: begin\n\t\t\to_m_ack <= i_s%d_ack;\n\t\tend\n" % (i, i)
ack_block_buf += "\t\tdefault: begin\n\t\t\to_m_ack <= 1\'h0;\n\t\tend\n\tendcase\nend\n\n"
#int in block
int_block_buf = "//int in from slave\n"
int_block_buf += "always @ (mem_select"
for i in range (0, num_mems):
int_block_buf += " or i_s%d_int" % (i)
int_block_buf += ") begin\n\tcase (mem_select)\n"
for i in range (0, num_mems):
int_block_buf += "\t\tMEM_SEL_%d: begin\n\t\t\to_m_int <= i_s%d_int;\n\t\tend\n" % (i, i)
int_block_buf += "\t\tdefault: begin\n\t\t\to_m_int <= 1\'h0;\n\t\tend\n\tendcase\nend\n\n"
buf = template.substitute( PORTS=port_buf,
MEM_SELECT=mem_select_buf,
ASSIGN=assign_buf,
DATA=data_block_buf,
ACK=ack_block_buf,
INT=int_block_buf,
MEM_PARAMS=param_buf)
buf = string.expandtabs(buf, 2)
return buf
def generate_wb_mem_interconnect(tags={}, user_paths=[], debug=False):
if "MEMORY" not in tags:
return ""
num_slaves = len(tags["MEMORY"].keys())
if debug: print "Number of slaves: %d" % num_slaves
buf = ""
#Allow errors to pass up to the calling class
directory = utils.get_local_verilog_path("nysa-verilog")
wb_i_loc = os.path.join(directory, "verilog", "wishbone", "interconnect",
"wishbone_mem_interconnect.v")
f = open(wb_i_loc, "r")
buf = f.read()
f.close()
template = Template(buf)
port_buf = ""
port_def_buf = ""
mem_select_buf = ""
assign_buf = ""
data_block_buf = ""
ack_block_buf = ""
int_block_buf = ""
param_buf = ""
#start with 1 to account for SDB
num_mems = 0
if (tags.has_key("MEMORY")):
#got a list of all the slaves to add to make room for
mem_list = tags["MEMORY"]
num_mems = num_mems + len(mem_list)
if num_mems == 0:
return ""
if debug:
"Memory Keys\n\n"
for key in tags["MEMORY"]:
print key + ":" + str(tags["MEMORY"][key])
print "\n\n"
slave_keywords = [
"SDB_ABI_VERSION_MAJOR", "SDB_ABI_VERSION_MINOR", "SDB_SIZE"
]
mem_offset = 0
#generate the parameters
for i in range(0, num_mems):
key = tags["MEMORY"].keys()[i]
absfilename = utils.find_rtl_file_location(
tags["MEMORY"][key]["filename"], user_paths)
#print "filename: %s" % absfilename
slave_tags = vutils.get_module_tags(filename=absfilename,
bus="wishbone",
keywords=slave_keywords,
project_tags=tags)
if debug:
print "slave tags: " + str(slave_tags)
mem_size = int(slave_tags["keywords"]["SDB_SIZE"].strip(), 0)
param_buf = param_buf + "parameter MEM_SEL_%d\t=\t%d;\n" % (i, i)
#param_buf = param_buf + "parameter MEM_OFFSET_%d\t=\t %d;\n" % (i, mem_offset)
param_buf = param_buf + "parameter MEM_OFFSET_%d\t=\t 32'h%08X;\n" % (
i, mem_offset)
param_buf = param_buf + "parameter MEM_SIZE_%d\t=\t 32'h%02X;\n" % (
i, mem_size)
mem_offset += mem_size
#generate the memory select logic
mem_select_buf = "reg [31:0] mem_select;\n"
mem_select_buf += "\n"
mem_select_buf += "always @(rst or i_m_adr or mem_select) begin\n"
mem_select_buf += "\tif (rst) begin\n"
mem_select_buf += "\t\t//nothing selected\n"
mem_select_buf += "\t\tmem_select <= 32'hFFFFFFFF;\n"
mem_select_buf += "\tend\n"
mem_select_buf += "\telse begin\n"
for i in range(num_mems):
if (i == 0):
mem_select_buf += "\t\tif "
else:
mem_select_buf += "\t\telse if "
mem_select_buf += "((i_m_adr >= MEM_OFFSET_%d) && (i_m_adr < (MEM_OFFSET_%d + MEM_SIZE_%d))) begin\n" % (
i, i, i)
mem_select_buf += "\t\t\tmem_select <= MEM_SEL_%d;\n" % i
mem_select_buf += "\t\tend\n"
mem_select_buf += "\t\telse begin\n"
mem_select_buf += "\t\t\tmem_select <= 32'hFFFFFFFF;\n"
mem_select_buf += "\t\tend\n"
mem_select_buf += "\tend\n"
mem_select_buf += "end\n"
#Ports
for i in range(0, num_slaves):
port_buf += "\t//Slave %d\n" % i
port_buf += "\toutput\t\t\t\t\t\t\to_s%d_we,\n" % i
port_buf += "\toutput\t\t\t\t\t\t\to_s%d_cyc,\n" % i
port_buf += "\toutput\t\t\t\t\t\t\to_s%d_stb,\n" % i
port_buf += "\toutput\t\t[3:0]\t\t\to_s%d_sel,\n" % i
port_buf += "\tinput\t\t\t\t\t\t\t\ti_s%d_ack,\n" % i
port_buf += "\toutput\t\t[31:0]\t\to_s%d_dat,\n" % i
port_buf += "\tinput\t\t\t[31:0]\t\ti_s%d_dat,\n" % i
port_buf += "\toutput\t\t[31:0]\t\to_s%d_adr,\n" % i
port_buf += "\tinput\t\t\t\t\t\t\t\ti_s%d_int" % i
#if this isn't the last slave add a comma
if (i < num_slaves - 1):
port_buf += ",\n"
port_buf += "\n"
#assign defines
for i in range(0, num_mems):
assign_buf += "assign o_s%d_we =\t(mem_select == MEM_SEL_%d) ? i_m_we: 1'b0;\n" % (
i, i)
assign_buf += "assign o_s%d_stb =\t(mem_select == MEM_SEL_%d) ? i_m_stb: 1'b0;\n" % (
i, i)
assign_buf += "assign o_s%d_sel =\t(mem_select == MEM_SEL_%d) ? i_m_sel: 4'b0;\n" % (
i, i)
assign_buf += "assign o_s%d_cyc =\t(mem_select == MEM_SEL_%d) ? i_m_cyc: 1'b0;\n" % (
i, i)
if i == 0:
assign_buf += "assign o_s%d_adr =\t(mem_select == MEM_SEL_%d) ? i_m_adr: 32'h0;\n" % (
i, i)
else:
assign_buf += "assign o_s%d_adr =\t(mem_select == MEM_SEL_%d) ? i_m_adr - MEM_OFFSET_%d: 32'h0;\n" % (
i, i, i)
assign_buf += "assign o_s%d_dat =\t(mem_select == MEM_SEL_%d) ? i_m_dat: 32'h0;\n" % (
i, i)
assign_buf += "\n"
#data in block
data_block_buf = "//data in from slave\n"
data_block_buf += "always @ (mem_select"
for i in range(0, num_mems):
data_block_buf += " or i_s%d_dat" % i
data_block_buf += ") begin\n\tcase (mem_select)\n"
for i in range(0, num_mems):
data_block_buf += "\t\tMEM_SEL_%d: begin\n\t\t\to_m_dat <= i_s%d_dat;\n\t\tend\n" % (
i, i)
data_block_buf += "\t\tdefault: begin\n\t\t\to_m_dat <= 32\'h0000;\n\t\tend\n\tendcase\nend\n\n"
#ack in block
ack_block_buf = "//ack in from mem slave\n"
ack_block_buf += "always @ (mem_select"
for i in range(0, num_mems):
ack_block_buf += " or i_s%d_ack" % i
ack_block_buf += ") begin\n\tcase (mem_select)\n"
for i in range(0, num_mems):
ack_block_buf += "\t\tMEM_SEL_%d: begin\n\t\t\to_m_ack <= i_s%d_ack;\n\t\tend\n" % (
i, i)
ack_block_buf += "\t\tdefault: begin\n\t\t\to_m_ack <= 1\'h0;\n\t\tend\n\tendcase\nend\n\n"
#int in block
int_block_buf = "//int in from slave\n"
int_block_buf += "always @ (mem_select"
for i in range(0, num_mems):
int_block_buf += " or i_s%d_int" % (i)
int_block_buf += ") begin\n\tcase (mem_select)\n"
for i in range(0, num_mems):
int_block_buf += "\t\tMEM_SEL_%d: begin\n\t\t\to_m_int <= i_s%d_int;\n\t\tend\n" % (
i, i)
int_block_buf += "\t\tdefault: begin\n\t\t\to_m_int <= 1\'h0;\n\t\tend\n\tendcase\nend\n\n"
buf = template.substitute(PORTS=port_buf,
MEM_SELECT=mem_select_buf,
ASSIGN=assign_buf,
DATA=data_block_buf,
ACK=ack_block_buf,
INT=int_block_buf,
MEM_PARAMS=param_buf)
buf = string.expandtabs(buf, 2)
return buf
def initialize_graph(self, debug=False):
"""Initializes the graph and project tags."""
# Clear any previous data.
#print "initialize graph"
self.gm.clear_graph()
# Set the bus type.
if self.config_dict["TEMPLATE"] == "wishbone_template.json":
self.set_bus_type("wishbone")
elif self.config_dict["TEMPLATE"] == "axi_template.json":
self.set_bus_type("axi")
else:
raise WishboneModelError("Template is not specified")
if "constraint_files" not in self.config_dict:
self.config_dict["constraint_files"] = []
if "board" in self.config_dict:
if len(self.config_dict["constraint_files"]) == 0:
cfiles = utils.get_constraint_filenames(self.config_dict["board"])
for cf in cfiles:
self.config_dict["constraint_files"].append(cf)
# Add the nodes that are always present.
self.gm.add_node("Host Interface", NodeType.HOST_INTERFACE)
self.gm.add_node("Master", NodeType.MASTER)
self.gm.add_node("Memory", NodeType.MEMORY_INTERCONNECT)
self.gm.add_node("Peripherals", NodeType.PERIPHERAL_INTERCONNECT)
self.add_slave("SDB", SlaveType.PERIPHERAL, slave_index=0)
# Attach all the appropriate nodes.
self.gm.connect_nodes(HOST_INTERFACE, MASTER)
self.gm.connect_nodes(MASTER, MEMORY_BUS)
self.gm.connect_nodes(MASTER, PERIPHERAL_BUS)
self.gm.connect_nodes(PERIPHERAL_BUS, SDB)
# Get module data for the SDB
# Attempt to load data from the tags.
#print "Config Dict: %s" % str(self.config_dict)
if "SLAVES" in self.config_dict:
for slave_name in self.config_dict["SLAVES"]:
if slave_name == "SDB":
continue
#Get the slave tags for this project
slave_project_tags = self.config_dict["SLAVES"][slave_name]
module_tags = {}
#Check to see if there is a file for this slave
if "filename" in slave_project_tags:
filename = slave_project_tags["filename"]
try:
filepath = utils.find_rtl_file_location(filename, self.paths)
module_tags = vutils.get_module_tags(filepath)
except IOError as ex:
#File not found, there is no associated tags with this
print "File: %s not found, passing in an empty module" % filename
uname = self.add_slave(slave_name,
SlaveType.PERIPHERAL,
module_tags = module_tags,
slave_project_tags = slave_project_tags)
# Load all the memory slaves.
if "MEMORY" in self.config_dict:
for slave_name in self.config_dict["MEMORY"]:
#Get the slave tags for thir project
slave_project_tags = self.config_dict["MEMORY"][slave_name]
module_tags = {}
#Check to see if there is a file for this slave
if "filename" in slave_project_tags:
filename = slave_project_tags["filename"]
try:
filepath = utils.find_rtl_file_location(filename, self.paths)
module_tags = vutils.get_module_tags(filepath)
except IOError as ex:
#File not found, there is no verilog core associated with this slave on this machine
print "File: %s not found, no verilog core associated with this module" % filename
uname = self.add_slave(slave_name,
SlaveType.MEMORY,
module_tags = module_tags,
slave_project_tags = slave_project_tags)
#Now that all the slaves are connected I need to connect any arbiters
if "SLAVES" in self.config_dict:
for slave_name in self.config_dict["SLAVES"]:
#print "working on slave: %s" % slave_name
slave_project_tags = self.config_dict["SLAVES"][slave_name]
if "BUS" not in slave_project_tags:
continue
#bus_dict = copy.deepcopy(slave_project_tags["BUS"])
from_slave_uname = self.get_unique_from_module_name(slave_name)
for arbiter in slave_project_tags["BUS"]:
slave_module_name = slave_project_tags["BUS"][arbiter]
#print "slave_module_name: %s" % slave_module_name
try:
to_slave_uname = self.get_unique_from_module_name(slave_module_name)
except gm.SlaveError as ex:
to_slave_uname = slave_module_name
slave_project_tags["BUS"][arbiter] = to_slave_uname
self.connect_arbiter(from_slave_uname, arbiter, to_slave_uname)
# Check if there is a host interface defined.
if "INTERFACE" in self.config_dict:
self.setup_host_interface()
if debug:
print ("Finish Initialize graph")
