def test_portgraph_vertex(): pg = PortGraph() assert_raises(InvalidPort, lambda: pg.vertex(0)) vid = pg.add_vertex() pid1 = pg.add_in_port(vid, 0) pid2 = pg.add_out_port(vid, 0) assert pg.vertex(pid1) == vid assert pg.vertex(pid2) == vid
def test_portgraph_big(): pg = PortGraph() vid1 = pg.add_vertex() pid11 = pg.add_out_port(vid1, "out") vid2 = pg.add_vertex() pid21 = pg.add_out_port(vid2, "out") vid3 = pg.add_vertex() pid31 = pg.add_in_port(vid3, "in1") pid32 = pg.add_in_port(vid3, "in2") pid33 = pg.add_out_port(vid3, "res") vid4 = pg.add_vertex() pid41 = pg.add_in_port(vid4, "in") eid1 = pg.connect(pid11, pid31) eid2 = pg.connect(pid21, pid32) pg.connect(pid33, pid41) assert pg.source_port(eid1) == pid11 assert pg.target_port(eid2) == pid32 assert set(pg.out_ports(vid1)) == {pid11} assert set(pg.in_ports(vid3)) == {pid31, pid32} assert set(pg.ports(vid3)) == {pid31, pid32, pid33} assert pg.is_in_port(pid31) assert pg.is_out_port(pid11) assert pg.vertex(pid11) == vid1 assert set(pg.connected_ports(pid11)) == {pid31} assert set(pg.connected_edges(pid21)) == {eid2} assert pg.out_port(vid1, "out") == pid11 assert pg.in_port(vid3, "in1") == pid31 assert_raises(InvalidPort, lambda: pg.connect(pid11, pid33)) pg.remove_port(pid33) assert set(pg.connected_ports(pid41)) == set() assert set(pg.out_edges(vid3)) == set() assert_raises(InvalidPort, lambda: pg.is_in_port(pid33))