def _cpu_reset(dut):
"""
The CPU reset value will be set and reset. The corresponding signal will
be observed.
"""
access = RegAccess(dut)
yield access.write_register(dest=MODULE_DI_ADDRESS,
src=SENDER_DI_ADDRESS,
word_width=16,
regaddr=DiPacket.SCM_REG.SYSRST.value,
value=2)
if dut.cpu_rst != 1:
raise TestFailure("CPU reset signal could not be set!")
yield access.write_register(dest=MODULE_DI_ADDRESS,
src=SENDER_DI_ADDRESS,
word_width=16,
regaddr=DiPacket.SCM_REG.SYSRST.value,
value=0)
if dut.cpu_rst != 0:
raise TestFailure("CPU reset signal could not be reset!")
def _activate_module(dut):
access = RegAccess(dut)
yield access.write_register(dest=MODULE_DI_ADDRESS,
src=SENDER_DI_ADDRESS,
word_width=16,
regaddr=DiPacket.BASE_REG.MOD_CS.value,
value=1)
def test_scm_baseregisters(dut):
"""
Read the 5 additional registers of the SCM and compares the response
with the desired value
"""
access = RegAccess(dut)
yield _init_dut(dut)
yield access.test_base_registers(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
mod_vendor=1, mod_type=1, mod_version=0,
can_stall=False)
def _activate_module(dut):
"""
Set the MOD_CS_ACTIVE bit in the Control and Status register to 1 to
enable emitting debug event packets.
"""
access = RegAccess(dut)
yield access.write_register(dest=MODULE_DI_ADDRESS,
src=SENDER_DI_ADDRESS,
word_width=16,
regaddr=DiPacket.BASE_REG.MOD_CS.value,
value=1)
def test_mam_base_registers(dut):
"""
Check if the base configuration registers have the expected values
"""
access = RegAccess(dut)
yield _init_dut(dut)
yield access.test_base_registers(MODULE_DI_ADDRESS,
SENDER_DI_ADDRESS,
mod_vendor=1,
mod_type=3,
mod_version=0,
can_stall=False)
def test_dem_uart_baseregisters(dut):
"""
Verify that the base configuration registers have the correct values.
"""
access = RegAccess(dut)
yield _init_dut(dut)
yield access.test_base_registers(MODULE_DI_ADDRESS,
SENDER_DI_ADDRESS,
mod_vendor=1,
mod_type=2,
mod_version=0,
can_stall=True)
def test_stm_base_registers(dut):
"""
Check if STM properly generates trace events
"""
access = RegAccess(dut)
yield _init_dut(dut)
yield access.test_base_registers(MODULE_DI_ADDRESS,
SENDER_DI_ADDRESS,
mod_vendor=1,
mod_type=4,
mod_version=0,
can_stall=True)
def test_access_base_registers(dut):
"""
Check if access to base registers works properly
"""
global _mod_vendor, _mod_type, _mod_version, _mod_event_dest_default, _can_stall, _max_reg_size
access = RegAccess(dut)
yield _init_dut(dut)
yield access.test_base_registers(MODULE_DI_ADDRESS,
SENDER_DI_ADDRESS,
mod_vendor=_mod_vendor,
mod_type=_mod_type,
mod_version=_mod_version,
can_stall=_can_stall)
def test_stm_activation(dut):
"""
Check if STM is handling the activation bit correctly
"""
access = RegAccess(dut)
yield _init_dut(dut)
dut._log.info("Check contents of MOD_CS")
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
DiPacket.BASE_REG.MOD_CS.value, 0)
yield _activate_module(dut)
dut._log.info("Check contents of MOD_CS")
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
DiPacket.BASE_REG.MOD_CS.value, 1)
def test_access_ext_registers(dut):
"""
Check if access to external registers works properly
"""
global _max_reg_size, _write_value, _req_addr, _req_width, _req_write
access = RegAccess(dut)
yield _init_dut(dut)
# start thread that works as debug module
debug_module = cocotb.fork(_debug_module_dummy(dut))
# different register widths to test
req_reg_width = [16, 32, 64, 128]
dut._log.info("Run write/read test of external registers")
# write and read 2000 random values to random external registers
for _ in range(200):
# addresses 0x0 - 0x1ff are handled internally. Test adresses 0x200 - 0xffff
_req_addr = random.randint(2**9, 2**16 - 1)
_req_width = req_reg_width[random.randint(0, 3)]
# ensure required width is not larger than MAX_REG_SIZE
_req_width = _req_width if _req_width <= _max_reg_size else _max_reg_size
_write_value = random.randint(0, 2**_req_width - 1)
_req_write = True
# write to register
yield access.write_register(dest=MODULE_DI_ADDRESS,
src=SENDER_DI_ADDRESS,
word_width=_req_width,
regaddr=_req_addr,
value=_write_value)
# wait a short random time
wait = random.randint(0, 10)
for _ in range(wait):
yield RisingEdge(dut.clk)
_req_write = False
# check if value was correctly written to debug module
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
_req_addr, _req_width, _write_value)
def test_scm_extended(dut):
"""
Read the 5 additional registers of the SCM and compares the response
with the desired value
"""
access = RegAccess(dut)
yield _init_dut(dut)
dut._log.info("Check contents of SYSTEM_VENDOR_ID")
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
DiPacket.SCM_REG.SYSTEM_VENDOR_ID.value, 1)
dut._log.info("Check contents of SYSTEM_DEVICE_ID")
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
DiPacket.SCM_REG.SYSTEM_DEVICE_ID.value, 1)
dut._log.info("Check contents of NUM_MOD")
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
DiPacket.SCM_REG.NUM_MOD.value, 1)
dut._log.info("Check contents of MAX_PKT_LEN")
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
DiPacket.SCM_REG.MAX_PKT_LEN.value, 8)
dut._log.info("Check contents of SYSRST")
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
DiPacket.SCM_REG.SYSRST.value, 0)
def test_dem_uart_activation(dut):
"""
Check if DEM_UART is handling the activation bit correctly
"""
access = RegAccess(dut)
yield _init_dut(dut)
dut._log.info("Check contents of MOD_CS")
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
DiPacket.BASE_REG.MOD_CS.value, 16, 0)
yield _activate_module(dut)
dut._log.info("Check contents of MOD_CS")
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
DiPacket.BASE_REG.MOD_CS.value, 16, 1)
_bus_to_di_fifo.clear()
write_thread = cocotb.fork(_bus_to_di_tx(dut, num_transfers=5))
read_thread = cocotb.fork(_bus_to_di_rx(dut, num_transfers=5))
yield read_thread.join()
yield access.write_register(dest=MODULE_DI_ADDRESS, src=SENDER_DI_ADDRESS,
word_width=16,
regaddr=DiPacket.BASE_REG.MOD_CS.value,
value=0)
write_thread = cocotb.fork(_bus_to_di_tx(dut, num_transfers=5))
# Wait one cycle to make sure the reader below doesn't accidentally try to
# receive parts of the RegAccess response packet
yield RisingEdge(dut.clk)
# Don't confuse users of this test when they see a warning message
dut._log.warning("The following warning 'packet receive timed out' is expected:")
packet = yield NocDiReader(dut, dut.clk).receive_packet(set_ready=True)
if packet:
raise TestFailure("Received packet while module was deactivated")
yield access.write_register(dest=MODULE_DI_ADDRESS, src=SENDER_DI_ADDRESS,
word_width=16,
regaddr=DiPacket.BASE_REG.MOD_CS.value,
value=1)
read_thread = cocotb.fork(_bus_to_di_rx(dut, num_transfers=5))
yield read_thread.join()
def test_mam_extended_registers(dut):
"""
Check if the extended configuration registers have the expected values
"""
access = RegAccess(dut)
yield _init_dut(dut)
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
DiPacket.MAM_REG.AW.value, 16,
dut.ADDR_WIDTH.value.integer)
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
DiPacket.MAM_REG.DW.value, 16,
dut.DATA_WIDTH.value.integer)
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
DiPacket.MAM_REG.REGIONS.value, 16,
dut.REGIONS.value.integer)
for region in range(0, dut.REGIONS.value.integer):
dut._log.info("Checking conf registers for region " + str(region))
region_basereg = 0x280 + region * 16
region_baseaddr_basereg = region_basereg
region_memsize_basereg = region_basereg + 4
baseaddr_exp = getattr(dut, "BASE_ADDR%d" % region).value.integer
memsize_exp = getattr(dut, "MEM_SIZE%d" % region).value.integer
# REGION*_BASEADDR_*
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
region_baseaddr_basereg, 16,
baseaddr_exp & 0xFFFF)
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
region_baseaddr_basereg + 1, 16,
(baseaddr_exp >> 16) & 0xFFFF)
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
region_baseaddr_basereg + 2, 16,
(baseaddr_exp >> 32) & 0xFFFF)
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
region_baseaddr_basereg + 3, 16,
(baseaddr_exp >> 48) & 0xFFFF)
# REGION*_MEMSIZE_*
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
region_memsize_basereg, 16,
memsize_exp & 0xFFFF)
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
region_memsize_basereg + 1, 16,
(memsize_exp >> 16) & 0xFFFF)
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
region_memsize_basereg + 2, 16,
(memsize_exp >> 32) & 0xFFFF)
yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS,
region_memsize_basereg + 3, 16,
(memsize_exp >> 48) & 0xFFFF)
def test_error_cases(dut):
"""
Trigger some error cases to check the module's behaviour.
"""
access = RegAccess(dut)
# different register widths to test
req_reg_width = [16, 32, 64, 128]
# internal address for error test case
int_reg = 0x100
# external address for error test case
ext_reg = 0x200
yield _init_dut(dut)
# set reg_err high as the "debug module" returns an error for all requests in this test
dut.reg_err <= 1
dut._log.info("Trigger register write response: error...")
dut._log.debug("by writing to illegal internal register address...")
for reg_size in req_reg_width:
if reg_size > _max_reg_size:
break
yield _trigger_reg_wr_req_err(dut, MODULE_DI_ADDRESS,
SENDER_DI_ADDRESS, reg_size, int_reg,
0xdead)
dut._log.debug(
"by writing to valid internal address with word width > 16 bit...")
for reg_size in req_reg_width[1:]:
if reg_size > _max_reg_size:
break
yield _trigger_reg_wr_req_err(dut, MODULE_DI_ADDRESS,
SENDER_DI_ADDRESS, reg_size, 4, 0xdead)
dut._log.debug(
"by writing to external register address with word width > MAX_REG_SIZE..."
)
widths = [w for w in req_reg_width if w > _max_reg_size]
if len(widths) == 0:
dut._log.debug("...no tests to be done.")
else:
for w in widths:
yield _trigger_reg_wr_req_err(dut, MODULE_DI_ADDRESS,
SENDER_DI_ADDRESS, w, ext_reg,
0xdead)
dut._log.debug("by raising reg_err from the debug module side...")
for reg_size in req_reg_width:
if reg_size > _max_reg_size:
break
yield _trigger_reg_wr_req_err(dut, MODULE_DI_ADDRESS,
SENDER_DI_ADDRESS, reg_size, ext_reg,
0xdead)
dut._log.info("Trigger register read response: error...")
dut._log.debug("by reading from illegal internal register address...")
for reg_size in req_reg_width:
if reg_size > _max_reg_size:
break
yield _trigger_reg_rd_req_err(dut, MODULE_DI_ADDRESS,
SENDER_DI_ADDRESS, reg_size, int_reg)
dut._log.debug(
"by reading from external register address with word width > MAX_REG_SIZE..."
)
widths = [w for w in req_reg_width if w > _max_reg_size]
if len(widths) == 0:
dut._log.debug("...no tests to be done.")
else:
for w in widths:
yield _trigger_reg_rd_req_err(dut, MODULE_DI_ADDRESS,
SENDER_DI_ADDRESS, w, ext_reg)
dut._log.debug("by raising reg_err from the debug module side...")
for reg_size in req_reg_width:
if reg_size > _max_reg_size:
break
yield _trigger_reg_rd_req_err(dut, MODULE_DI_ADDRESS,
SENDER_DI_ADDRESS, reg_size, ext_reg)