def _add_chip_lpg_reqs(lpg_parameters, chip, lpg_sdram, sdrams, cores,
iptags):
# pylint: disable=too-many-arguments
sdram_reqs = 0
core_reqs = 0
for lpg_params in lpg_parameters:
if (lpg_params.board_address is None
or lpg_params.board_address == chip.ip_address):
sdram_reqs += lpg_sdram
core_reqs += 1
iptags.append(
SpecificBoardTagResource(
board=chip.ip_address,
ip_address=lpg_params.hostname,
port=lpg_params.port,
strip_sdp=lpg_params.strip_sdp,
tag=lpg_params.tag,
traffic_identifier=LPG.TRAFFIC_IDENTIFIER))
if sdram_reqs:
sdrams.append(
SpecificChipSDRAMResource(chip, ConstantSDRAM(sdram_reqs)))
if core_reqs:
cores.append(CoreResource(chip, core_reqs))
def test_1_chip_over_pre_allocated(self):
machine = virtual_machine(width=8, height=8)
graph = ApplicationGraph("Test")
partitioner = SplitterPartitioner()
# add graph vertices which reside on 0,0
for _ in range(0, 13):
vertex = SimpleTestVertex(
constraints=[ChipAndCoreConstraint(x=0, y=0)],
n_atoms=1)
vertex.splitter = SplitterSliceLegacy()
graph.add_vertex(vertex)
# add pre-allocated resources for cores on 0,0
core_pre = CoreResource(chip=machine.get_chip_at(0, 0), n_cores=5)
pre_allocated_res = PreAllocatedResourceContainer(
core_resources=[core_pre])
# run partitioner that should go boom
try:
partitioner(graph, machine, plan_n_time_steps=None,
pre_allocated_resources=pre_allocated_res)
raise Exception("should have blown up here")
except PacmanInvalidParameterException:
pass
def test_n_cores_available(self):
machine = virtual_machine(width=2, height=2, n_cpus_per_chip=18)
chip = machine.get_chip_at(0, 0)
preallocated_resources = PreAllocatedResourceContainer(
specific_core_resources=[
SpecificCoreResource(chip=chip, cores=[1])
],
core_resources=[CoreResource(chip=chip, n_cores=2)])
tracker = ResourceTracker(
machine,
plan_n_timesteps=None,
preallocated_resources=preallocated_resources)
# Should be 14 cores = 18 - 1 monitor - 1 specific core - 2 other cores
self.assertEqual(tracker._n_cores_available(chip, (0, 0), None), 14)
# Should be 0 since the core is already pre allocated
self.assertEqual(tracker._n_cores_available(chip, (0, 0), 1), 0)
# Should be 1 since the core is not pre allocated
self.assertEqual(tracker._n_cores_available(chip, (0, 0), 2), 1)
# Should be 0 since the core is monitor
self.assertEqual(tracker._n_cores_available(chip, (0, 0), 0), 0)
# Allocate a core
tracker._allocate_core(chip, (0, 0), 2)
# Should be 13 cores as one now allocated
self.assertEqual(tracker._n_cores_available(chip, (0, 0), None), 13)
def __call__(self,
machine,
n_machine_time_steps,
n_samples_per_recording,
sampling_frequency,
time_scale_factor,
machine_time_step,
pre_allocated_resources=None):
"""
:param pre_allocated_resources: other preallocated resources
:param machine: the SpiNNaker machine as discovered
:param n_machine_time_steps: the number of machine\
time steps used by the simulation during this phase
:param n_samples_per_recording: how many samples between record entries
:param sampling_frequency: the frequency of sampling
:param time_scale_factor: the time scale factor
:param machine_time_step: the machine time step
:return: preallocated resources
"""
# pylint: disable=too-many-arguments
progress_bar = ProgressBar(
machine.n_chips, "Preallocating resources for chip power monitor")
# store how much SDRAM the power monitor uses per core
resources = ChipPowerMonitor.get_resources(
n_machine_time_steps=n_machine_time_steps,
n_samples_per_recording=n_samples_per_recording,
sampling_frequency=sampling_frequency,
time_scale_factor=time_scale_factor,
time_step=machine_time_step)
# for every Ethernet connected chip, get the resources needed by the
# live packet gatherers
sdrams = list()
cores = list()
for chip in progress_bar.over(machine.chips):
sdrams.append(
SpecificChipSDRAMResource(chip, resources.sdram.get_value()))
cores.append(CoreResource(chip, 1))
# create preallocated resource container
cpm_pre_allocated_resource_container = PreAllocatedResourceContainer(
specific_sdram_usage=sdrams, core_resources=cores)
# add other preallocated resources
if pre_allocated_resources is not None:
cpm_pre_allocated_resource_container.extend(
pre_allocated_resources)
# return preallocated resources
return cpm_pre_allocated_resource_container
def _add_chip_lpg_reqs(lpg_parameters, chip, lpg_sdram, sdrams, cores):
sdram_reqs = 0
core_reqs = 0
for lpg_params in lpg_parameters:
if (lpg_params.board_address is None
or lpg_params.board_address == chip.ip_address):
sdram_reqs += lpg_sdram
core_reqs += 1
if sdram_reqs > 0:
sdrams.append(SpecificChipSDRAMResource(chip, sdram_reqs))
if core_reqs > 0:
cores.append(CoreResource(chip, core_reqs))
def _handle_second_monitor_support(cores, sdrams, machine, progress):
""" Adds the second monitor preallocations, which reflect the\
reinjector and data extractor support
:param list(~.CoreResource) cores: the storage of core requirements
:param ~.Machine machine: the spinnMachine instance
:param ~.ProgressBar progress: the progress bar to operate one
"""
extra_usage = \
ExtraMonitorSupportMachineVertex.static_resources_required()
for chip in progress.over(machine.chips):
cores.append(CoreResource(chip=chip, n_cores=1))
sdrams.append(
SpecificChipSDRAMResource(chip=chip,
sdram_usage=extra_usage.sdram))
def __call__(
self, machine, n_samples_per_recording,
sampling_frequency, time_scale_factor, machine_time_step,
pre_allocated_resources=None):
"""
:param ~.PreAllocatedResourceContainer pre_allocated_resources:
:param ~.Machine machine:
:param int n_samples_per_recording:
:param int sampling_frequency:
:param int time_scale_factor:
:param int machine_time_step:
:rtype: ~.PreAllocatedResourceContainer
"""
# pylint: disable=too-many-arguments
progress_bar = ProgressBar(
machine.n_chips, "Preallocating resources for chip power monitor")
# store how much SDRAM the power monitor uses per core
resources = ChipPowerMonitorMachineVertex.get_resources(
n_samples_per_recording=n_samples_per_recording,
sampling_frequency=sampling_frequency,
time_scale_factor=time_scale_factor,
time_step=machine_time_step)
# for every Ethernet connected chip, get the resources needed by the
# live packet gatherers
sdrams = list()
cores = list()
for chip in progress_bar.over(machine.chips):
sdrams.append(
SpecificChipSDRAMResource(chip, resources.sdram))
cores.append(CoreResource(chip, 1))
# create preallocated resource container
cpm_pre_allocated_resource_container = PreAllocatedResourceContainer(
specific_sdram_usage=sdrams, core_resources=cores)
# add other preallocated resources
if pre_allocated_resources is not None:
cpm_pre_allocated_resource_container.extend(
pre_allocated_resources)
# return preallocated resources
return cpm_pre_allocated_resource_container
def _handle_packet_gathering_support(sdrams, cores, tags, machine,
progress, n_cores_to_allocate):
""" Adds the packet gathering functionality tied into the data\
extractor within each chip
:param list(~.SpecificChipSDRAMResource) sdrams:
the preallocated SDRAM requirement for these vertices
:param list(~.CoreResource) cores:
the preallocated cores requirement for these vertices
:param list(~.SpecificBoardIPtagResource) tags:
the preallocated tags requirement for these vertices
:param ~.Machine machine: the spinnMachine instance
:param ~.ProgressBar progress: the progress bar to update as needed
:param int n_cores_to_allocate:
how many packet gathers to allocate per chip
"""
# pylint: disable=too-many-arguments
# get resources from packet gatherer
resources = DataSpeedUpPacketGatherMachineVertex.\
static_resources_required()
# locate Ethernet connected chips that the vertices reside on
for ethernet_connected_chip in \
progress.over(machine.ethernet_connected_chips,
finish_at_end=False):
# do resources. SDRAM, cores, tags
sdrams.append(
SpecificChipSDRAMResource(chip=ethernet_connected_chip,
sdram_usage=resources.sdram))
cores.append(
CoreResource(chip=ethernet_connected_chip,
n_cores=n_cores_to_allocate))
tags.append(
SpecificBoardIPtagResource(
board=ethernet_connected_chip.ip_address,
ip_address=resources.iptags[0].ip_address,
port=resources.iptags[0].port,
strip_sdp=resources.iptags[0].strip_sdp,
tag=resources.iptags[0].tag,
traffic_identifier=resources.iptags[0].traffic_identifier))
def test_1_chip_under_pre_allocated(self):
machine = VirtualMachine(width=8, height=8)
graph = ApplicationGraph("Test")
partitioner = PartitionAndPlacePartitioner()
# add graph vertices which reside on 0,0
for _ in range(0, 13):
graph.add_vertex(
SimpleTestVertex(constraints=[ChipAndCoreConstraint(x=0, y=0)],
n_atoms=1))
# add pre-allocated resources for cores on 0,0
core_pre = CoreResource(chip=machine.get_chip_at(0, 0), n_cores=4)
pre_allocated_res = PreAllocatedResourceContainer(
core_resources=[core_pre])
# run partitioner that should go boom
try:
partitioner(graph, machine, pre_allocated_res)
except Exception:
raise Exception("should have blown up here")
def _add_chip_lpg_reqs(lpg_parameters, chip, lpg_sdram, sdrams, cores,
iptags):
"""
:param lpg_parameters:
:type lpg_parameters:
dict(LivePacketGatherParameters,
list(tuple(~.AbstractVertex, list(str))))
:param ~.Chip chip:
:param int lpg_sdram:
:param list(~.SpecificChipSDRAMResource) sdrams:
:param list(~.CoreResource) cores:
:param list(~.SpecificBoardTagResource) iptags:
"""
# pylint: disable=too-many-arguments
sdram_reqs = 0
core_reqs = 0
for lpg_params in lpg_parameters:
if (lpg_params.board_address is None
or lpg_params.board_address == chip.ip_address):
sdram_reqs += lpg_sdram
core_reqs += 1
iptags.append(
SpecificBoardTagResource(
board=chip.ip_address,
ip_address=lpg_params.hostname,
port=lpg_params.port,
strip_sdp=lpg_params.strip_sdp,
tag=lpg_params.tag,
traffic_identifier=LPG.TRAFFIC_IDENTIFIER))
if sdram_reqs:
sdrams.append(
SpecificChipSDRAMResource(chip, ConstantSDRAM(sdram_reqs)))
if core_reqs:
cores.append(CoreResource(chip, core_reqs))
def test_added_pre_res(self):
machine = virtual_machine(width=12, height=12, with_wrap_arounds=True)
default_params = {
'use_prefix': False,
'key_prefix': None,
'prefix_type': None,
'message_type': EIEIOType.KEY_32_BIT,
'right_shift': 0,
'payload_as_time_stamps': True,
'use_payload_prefix': True,
'payload_prefix': None,
'payload_right_shift': 0,
'number_of_packets_sent_per_time_step': 0,
'hostname': None,
'port': None,
'strip_sdp': None,
'board_address': None,
'tag': None}
# data stores needed by algorithm
live_packet_gatherers = dict()
extended = dict(default_params)
extended.update({'partition_id': "EVENTS"})
default_params_holder = LivePacketGatherParameters(**extended)
live_packet_gatherers[default_params_holder] = list()
# create pre res
sdram_requirements = {machine.get_chip_at(2, 2): 30000,
machine.get_chip_at(7, 7): 50000}
core_requirements = {machine.get_chip_at(3, 3): 2}
sdrams = list()
cores = list()
for chip in sdram_requirements:
sdrams.append(SpecificChipSDRAMResource(
chip, ConstantSDRAM(sdram_requirements[chip])))
for chip in core_requirements:
cores.append(CoreResource(chip, core_requirements[chip]))
pre_pre_res = PreAllocatedResourceContainer(
core_resources=cores, specific_sdram_usage=sdrams)
# run pre allocator
pre_alloc = PreAllocateResourcesForLivePacketGatherers()
pre_res = pre_alloc(
live_packet_gatherer_parameters=live_packet_gatherers,
machine=machine, pre_allocated_resources=pre_pre_res)
locs = list()
locs.append((0, 0))
locs.append((4, 8))
locs.append((8, 4))
locs.append((2, 2))
locs.append((7, 7))
# verify sdram
sdrams = pre_res.specific_sdram_usage
for sdram in sdrams:
locs.remove((sdram.chip.x, sdram.chip.y))
if sdram.sdram_usage.get_total_sdram(0) != \
LivePacketGatherMachineVertex.get_sdram_usage():
self.assertIn(sdram.chip.x, (2, 7))
self.assertIn(sdram.chip.y, (2, 7))
self.assertEqual(sdram.chip.x, sdram.chip.y)
if sdram.chip.x == 2 and sdram.chip.y == 2:
self.assertEqual(sdram.sdram_usage.get_total_sdram(0),
30000)
elif sdram.chip.x == 7 and sdram.chip.y == 7:
self.assertEqual(sdram.sdram_usage.get_total_sdram(0),
50000)
self.assertEqual(len(locs), 0)
locs = list()
locs.append((0, 0))
locs.append((4, 8))
locs.append((8, 4))
locs.append((3, 3))
# verify cores
cores = pre_res.core_resources
for core in cores:
locs.remove((core.chip.x, core.chip.y))
if core.n_cores != 1:
self.assertEqual(core.chip.x, 3)
self.assertEqual(core.chip.y, 3)
self.assertEqual(core.n_cores, 2)
self.assertEqual(len(locs), 0)
# verify specific cores
self.assertEqual(len(pre_res.specific_core_resources), 0)