def build(self,
board: pcbnew.BOARD,
external_signals: dict[str, pcbnew.NETINFO_ITEM] = {},
path: list[str] = []):
# Populate signal map creating new signals where required
local_signals = {}
for name in self.public_signals:
if name in external_signals:
local_signals[name] = external_signals[name]
else:
net = pcbnew.NETINFO_ITEM(board, "/".join(
(*path, self.id, name)))
board.Add(net)
local_signals[name] = net
for name in self.private_signals:
net = pcbnew.NETINFO_ITEM(board, "/".join((*path, self.id, name)))
board.Add(net)
local_signals[name] = net
# TODO: Warn about unused signals?
for component, signal_mapping in self.components:
component.build(
board, {
inner_name: local_signals[signal_name]
for (inner_name, signal_name) in signal_mapping.items()
}, (*path, self.id))
def build(self):
board = pcbnew.BOARD()
# outline
PcbPolygon(self.outline).build(board)
# Add holes
for h in self.holes:
h.build(board)
# Add ground plane
signals = {}
if self.fill_name:
fill_net = pcbnew.NETINFO_ITEM(board, self.fill_name)
board.Add(fill_net)
signals[self.fill_name] = fill_net
item = pcbnew.ZONE(board, False)
poly = pcbnew.wxPoint_Vector()
for x, y in self.outline.exterior.coords:
poly.append(pcbnew.wxPointMM(x, y))
item.AddPolygon(poly)
item.SetNet(fill_net)
lset = pcbnew.LSET()
lset.AddLayer(pcbnew.F_Cu)
lset.AddLayer(pcbnew.B_Cu)
item.SetLayerSet(lset)
board.Add(item)
for component in self.components:
component.build(board, signals)
return board
def AddNet(self):
netname = self.m_txtNetName.GetLineText(0)
if netname == "":
wx.MessageBox("Set a netname")
return
if self.SelectedModule == None or self.SelectedPad == None:
wx.MessageBox("Select a module and a pad")
return
netcode = -1
for mod in self.modules:
pads = mod.Pads()
for pad in pads:
net = pad.GetNet()
nc = net.GetNet()
if nc > netcode:
netcode = nc
netcode += 1
newnet = pcbnew.NETINFO_ITEM(self.board, netname, netcode)
self.board.Add(newnet)
self.SelectedPad.SetNet(newnet)
wx.MessageBox("Net %s assigned to: %s->%s" %
(netname, self.SelectedModule.GetReference(),
self.SelectedPad.GetName()))
pcbnew.Refresh()
self.Destroy()
def _makeNetNamesUnique(self, board):
prefix = self._uniquePrefix()
originalNetNames = collectNetNames(board)
netinfo = board.GetNetInfo()
newNetMapping = {"": netinfo.GetNetItem("")}
for name in originalNetNames:
newNet = pcbnew.NETINFO_ITEM(board, prefix + name)
newNetMapping[name] = newNet
board.Add(newNet)
remapNets(board.GetPads(), newNetMapping)
remapNets(board.GetTracks(), newNetMapping)
remapNets(board.Zones(), newNetMapping)
for name in originalNetNames:
if name != "":
board.RemoveNative(netinfo.GetNetItem(name))
def renameNets(board, renamer):
"""
Given a board and renaming function (taking original name, returning new
name) renames the nets
"""
originalNetNames = collectNetNames(board)
netinfo = board.GetNetInfo()
newNetMapping = {"": netinfo.GetNetItem("")}
for name in originalNetNames:
newNet = pcbnew.NETINFO_ITEM(board, renamer(name))
newNetMapping[name] = newNet
board.Add(newNet)
remapNets(board.GetPads(), newNetMapping)
remapNets(board.GetTracks(), newNetMapping)
remapNets(board.Zones(), newNetMapping)
for name in originalNetNames:
if name != "":
board.RemoveNative(netinfo.GetNetItem(name))
def ensure_net(board, net_name):
net = pcbnew.NETINFO_ITEM(board, net_name)
board.Add(net)
return net.GetNet() # luckily, it makes sure there are no duplicates
def kinet2pcb(netlist_origin, brd_filename):
"""Create a .kicad_pcb from a KiCad netlist file."""
# Get the global and local fp-lib-table file URIs.
fp_libs = LibURIs(get_global_fp_lib_table_fn(),
os.path.join(".", "fp-lib-table"))
# Create a blank KiCad PCB.
brd = pcbnew.BOARD()
# Get the netlist.
if isinstance(netlist_origin, type('')):
# Parse the netlist into an object if given a file name string.
netlist = kinparse.parse_netlist(netlist_origin)
else:
# otherwise, the netlist is already an object that can be processed directly.
netlist = netlist_origin
# Add the components in the netlist to the PCB.
for part in netlist.parts:
# Get the library and footprint name for the part.
fp_lib, fp_name = part.footprint.split(":")
# Get the URI of the library directory.
lib_uri = fp_libs[fp_lib]
# Create a module from the footprint file.
fp = pcbnew.FootprintLoad(lib_uri, fp_name)
# Set the module parameters based on the part data.
#import pdb; pdb.set_trace()
fp.SetParent(brd)
fp.SetReference(part.ref)
fp.SetValue(part.value)
# fp.SetTimeStamp(part.sheetpath.tstamps)
try:
fp.SetPath(part.sheetpath.names)
except AttributeError:
pass
# Add the module to the PCB.
brd.Add(fp)
# Add the nets in the netlist to the PCB.
cnct = brd.GetConnectivity()
for net in netlist.nets:
# Create a net with the current net name.
pcb_net = pcbnew.NETINFO_ITEM(brd, net.name)
# Add the net to the PCB.
brd.Add(pcb_net)
# Connect the part pins on the netlist net to the PCB net.
for pin in net.pins:
# Find the PCB module pad for the current part pin.
module = brd.FindModuleByReference(pin.ref)
pad = module.FindPadByName(pin.num)
# Connect the pad to the PCB net.
cnct.Add(pad)
pad.SetNet(pcb_net)
# Recalculate the PCB part and net data.
brd.BuildListOfNets()
cnct.RecalculateRatsnest()
pcbnew.Refresh()
# Place the board parts into non-overlapping areas that follow the design hierarchy.
hierplace.hier_place(brd)
# Save the PCB into the KiCad PCB file.
pcbnew.SaveBoard(brd_filename, brd)