def test_LW_SW( dump_vcd ): temp = copy.deepcopy(template_inputs) temp['regfile_w'] = 0x1 temp['data_s'] = 0x2 temp['operand_s'] = 0x3 temp['rX_address'] = 0x1 temp['rY_address'] = 0x1 temp['rZ_address'] = 0x1 temp['word_r'] = 0xFF temp['pc*'] = 0x2 model = Datapath() model._auto_init() test_vector = [gen_table_header(temp)] test_vector.append(gen_table_row(temp)[:]) temp['regfile_w'] = 0x0 temp['word_r'] = 0x0 temp['pc*'] = 0x3 temp['word_w*'] = 0xFF temp['word_a*'] = '?' test_vector.append(gen_table_row(temp)[:]) run_test_vector_sim(model, test_vector, dump_vcd)
def test_jump_type( dump_vcd ): temp = copy.deepcopy(template_inputs) test_vector = [gen_table_header(temp)] test_vector = test_vector + fill_registers(temp) temp['rX_address'] = 0x1 temp['rY_address'] = 0x1 temp['data_s'] = 0x4 temp['pc_s'] = 0x1 temp['immediate'] = 0x0F temp['pc*'] = 0xA temp['word_a*'] = '?' temp['word_w*'] = '?' temp['alu_s'] = 0x6 test_vector.append(gen_table_row(temp)[:]) temp = copy.deepcopy(template_inputs) temp['pc*'] = 0xA + 0xF test_vector.append(gen_table_row(temp)[:]) print test_vector model = Datapath() model._auto_init() run_test_vector_sim(model, test_vector, dump_vcd)
def run_word(row, dump_vcd):
output = ["", []]
for key, value in row.iteritems():
output[0] = output[0] + key + ' '
output[1].append(value)
run_test_vector_sim(Decoder(), output, dump_vcd)
def test_immgen( test_verilog, dump_vcd ):
header_str = \
( "imm_type", "inst",
"imm*" )
run_test_vector_sim( ImmGenRTL(), [ header_str,
# imm_type inst imm
[ 0, 0b11111111111100000000000000000000, 0b11111111111111111111111111111111], # I-imm
[ 0, 0b00000000000011111111111111111111, 0b00000000000000000000000000000000], # I-imm
[ 0, 0b01111111111100000000000000000000, 0b00000000000000000000011111111111], # I-imm
[ 0, 0b11111111111000000000000000000000, 0b11111111111111111111111111111110], # I-imm
[ 1, 0b11111110000000000000111110000000, 0b11111111111111111111111111111111], # S-imm
[ 1, 0b00000001111111111111000001111111, 0b00000000000000000000000000000000], # S-imm
[ 1, 0b01111110000000000000111110000000, 0b00000000000000000000011111111111], # S-imm
[ 1, 0b11111110000000000000111100000000, 0b11111111111111111111111111111110], # S-imm
[ 2, 0b11111110000000000000111110000000, 0b11111111111111111111111111111110], # B-imm
[ 2, 0b00000001111111111111000001111111, 0b00000000000000000000000000000000], # B-imm
[ 2, 0b11000000000000000000111100000000, 0b11111111111111111111010000011110], # B-imm
[ 3, 0b11111111111111111111000000000000, 0b11111111111111111111000000000000], # U-imm
[ 3, 0b00000000000000000000111111111111, 0b00000000000000000000000000000000], # U-imm
[ 4, 0b11111111111111111111000000000000, 0b11111111111111111111111111111110], # J-imm
[ 4, 0b00000000000000000001111111111111, 0b00000000000000000001000000000000], # J-imm
[ 4, 0b01000000000010011001000000000000, 0b00000000000010011001010000000000], # J-imm
], dump_vcd, test_verilog )
def test_simple(i):
#-----------------------------------------------------------------------
# Inner
#-----------------------------------------------------------------------
#
# Problematic connection:
#
# top.a -> middle.a[0:2] -> middle.a -> middle.a[0] -> inner.a
# 0 -> middle.a[2:4] -> ^
#
# A slice_cb() function is generated for top.a => middle.a[0:2].
# This is attached to top.a and is responsible for writing
# middle.a[0:2].
#
# A slice_cb() is also needed for middle.a[0] => inner.a.
# For **working** runs, this slice_cb seems to be attached to the slice
# middle.a[0:2]. This is odd since I would expect it to be attached to
# middle.a and triggered which middle.a[0:2] writes middle.a!
#
class Inner(Model):
def __init__(s):
s.a = InPort(1)
s.out = OutPort(1)
@s.combinational
def logic():
s.out.value = s.a
class Middle(Model):
def __init__(s):
s.a = InPort(4)
s.out = OutPort(1)
s.inner = Inner()
s.connect_dict({
s.inner.a: s.a[0],
s.inner.out: s.out,
})
class Top(Model):
def __init__(s):
s.a = InPort(2)
s.out = OutPort(1)
s.middle = Middle()
s.connect(s.a, s.middle.a[0:2])
s.connect(0, s.middle.a[2:4])
s.connect(s.out, s.middle.out)
#-----------------------------------------------------------------------
# Inner
#-----------------------------------------------------------------------
run_test_vector_sim(Top(), [
('a out*'),
[1, 1],
[2, 0],
[3, 1],
])
def test_overflow( dump_vcd ):
run_test_vector_sim( RegIncr(), [
('in_ out*'),
[ 0x00, '?' ],
[ 0xfe, 0x01 ],
[ 0xff, 0xff ],
[ 0x00, 0x00 ],
], dump_vcd )
def test_overflow(dump_vcd):
run_test_vector_sim(RegIncr(), [
('in_ out*'),
[0x00, '?'],
[0x0, 0x0],
[0xFF, 0xFF],
[0xFE, 0x1],
], dump_vcd)
def test_large(dump_vcd):
run_test_vector_sim(RegIncr(), [
('in_ out*'),
[0xa0, '?'],
[0xb3, 0xa1],
[0xc6, 0xb4],
[0x00, 0xc7],
], dump_vcd)
def test_student_random(dump_vcd):
test_vector_table = [("in_", "out*")]
last_result = "?"
for i in xrange(20):
rand_value = Bits(8, random.randint(0, 0x0F))
test_vector_table.append([rand_value, last_result])
last_result = Bits(8, rand_value + 1)
run_test_vector_sim(RegIncr(), test_vector_table, dump_vcd)
def test_basic():
run_test_vector_sim(
PortArrayBug(), [
('base offset out[0]* out[1]*'),
(0, 1, 0, 1),
(1, 1, 1, 2),
],
test_verilog=True)
def test_small_random(dump_vcd):
test_vector_table = [('in_', 'out*')]
last_result = '?'
for i in xrange(20):
rand_value = Bits(8, random.randint(0, 0x16))
test_vector_table.append([rand_value, last_result])
last_result = Bits(8, rand_value + 1)
run_test_vector_sim(RegIncr(), test_vector_table, dump_vcd)
def test_overflow(dump_vcd):
run_test_vector_sim(RegIncr(), [
('in_ out*'),
[0x00, '?'],
[0xfe, 0x01],
[0xff, 0xff],
[0x00, 0x00],
], dump_vcd)
def test_custom(dump_vcd):
run_test_vector_sim(RegIncr(), [
('in_ out*'),
[0xaa, '?'],
[0xbb, 0xab],
[0xaf, 0xbc],
[0x00, 0xb0],
], dump_vcd)
def test_small( dump_vcd ):
run_test_vector_sim( RegIncr(), [
('in_ out*'),
[ 0x00, '?' ],
[ 0x03, 0x01 ],
[ 0x06, 0x04 ],
[ 0x00, 0x07 ],
], dump_vcd )
def test_large( dump_vcd ):
run_test_vector_sim( RegIncr(), [
('in_ out*'),
[ 0xa0, '?' ],
[ 0xb3, 0xa1 ],
[ 0xc6, 0xb4 ],
[ 0x00, 0xc7 ],
], dump_vcd )
def test_peter(dump_vcd):
run_test_vector_sim(RegIncr(), [
('in_ out*'),
[0x00, '?'],
[0x01, 0x01],
[0x02, 0x02],
[0x03, 0x03],
], dump_vcd)
def test_small(dump_vcd):
run_test_vector_sim(RegIncr(), [
('in_ out*'),
[0x00, '?'],
[0x03, 0x01],
[0x06, 0x04],
[0x00, 0x07],
], dump_vcd)
def test_small_random( dump_vcd ):
test_vector_table = [('in_', 'out*')]
last_result = '?'
for i in xrange(20):
rand_value = Bits( 8, random.randint(0, 0x16) )
test_vector_table.append( [ rand_value, last_result ] )
last_result = Bits( 8, rand_value + 1 )
run_test_vector_sim( RegIncr(), test_vector_table, dump_vcd )
def test_basic(dump_vcd, test_verilog):
run_test_vector_sim(MinMaxUnit(), [
('in0 in1 min_* max_*'),
[0x00, 0x00, 0x00, 0x00],
[0x04, 0x03, 0x03, 0x04],
[0x09, 0x06, 0x06, 0x09],
[0x0a, 0x0f, 0x0a, 0x0f],
[0xff, 0x10, 0x10, 0xff],
], dump_vcd, test_verilog)
def test_alu_fn_ltu( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 14, 0x00000000, '?', '?', 0 ],
[ 0x0ffaa660, 0x00012304, 14, 0x00000000, '?', '?', 0 ],
[ 0x00132050, 0xd6620040, 14, 0x00000000, '?', '?', 1 ],
[ 0xfff0a440, 0x00004450, 14, 0x00000000, '?', '?', 0 ],
[ 0xfeeeeaa3, 0xf4650000, 14, 0x00000000, '?', '?', 0 ],
], dump_vcd, test_verilog )
def test_basic( dump_vcd, test_verilog ):
run_test_vector_sim( MinMaxUnit(), [
('in0 in1 min_* max_*'),
[ 0x00, 0x00, 0x00, 0x00 ],
[ 0x04, 0x03, 0x03, 0x04 ],
[ 0x09, 0x06, 0x06, 0x09 ],
[ 0x0a, 0x0f, 0x0a, 0x0f ],
[ 0xff, 0x10, 0x10, 0xff ],
], dump_vcd, test_verilog )
def test_small( dump_vcd ):
run_test_vector_sim( RegIncr2stage(), [
('in_ out*'),
[ 0x00, '?' ],
[ 0x03, '?' ],
[ 0x06, 0x02 ],
[ 0x00, 0x05 ],
[ 0x00, 0x08 ],
], dump_vcd )
def test_alu_jalr( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 10, 0x00000000, '?', '?', '?' ],
[ 0x0ffaa660, 0x00000304, 10, 0x0ffaa964, '?', '?', '?' ],
[ 0x00132050, 0x00000045, 10, 0x00132094, '?', '?', '?' ],
[ 0xfff0a440, 0x00000fff, 10, 0xfff0b43e, '?', '?', '?' ],
[ 0xfeeeeaa3, 0x000004de, 10, 0xfeeeef80, '?', '?', '?' ],
], dump_vcd, test_verilog )
def test_alu_and( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 2, 0x00000000, '?', '?', '?' ],
[ 0x0ffaa660, 0x00012304, 2, 0x00002200, '?', '?', '?' ],
[ 0x00132050, 0xd6620040, 2, 0x00020040, '?', '?', '?' ],
[ 0xfff0a440, 0x00004450, 2, 0x00000440, '?', '?', '?' ],
[ 0xffffffff, 0xffffffff, 2, 0xffffffff, '?', '?', '?' ],
], dump_vcd, test_verilog )
def test_alu_xor( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 4, 0x00000000, '?', '?', '?' ],
[ 0x0ffaa660, 0x00012304, 4, 0x0ffb8564, '?', '?', '?' ],
[ 0x00132050, 0xd6620040, 4, 0xd6712010, '?', '?', '?' ],
[ 0xfff0a440, 0x00004450, 4, 0xfff0e010, '?', '?', '?' ],
[ 0xffffffff, 0xffffffff, 4, 0x00000000, '?', '?', '?' ],
], dump_vcd, test_verilog )
def test_large( dump_vcd ):
run_test_vector_sim( RegIncr2stage(), [
('in_ out*'),
[ 0xa0, '?' ],
[ 0xb3, '?' ],
[ 0xc6, 0xa2 ],
[ 0x00, 0xb5 ],
[ 0x00, 0xc8 ],
], dump_vcd )
def test_small(dump_vcd):
run_test_vector_sim(RegIncr2stage(), [
('in_ out*'),
[0x00, '?'],
[0x03, '?'],
[0x06, 0x02],
[0x00, 0x05],
[0x00, 0x08],
], dump_vcd)
def test_large(dump_vcd):
run_test_vector_sim(RegIncr2stage(), [
('in_ out*'),
[0xa0, '?'],
[0xb3, '?'],
[0xc6, 0xa2],
[0x00, 0xb5],
[0x00, 0xc8],
], dump_vcd)
def test_basic( dump_vcd ):
run_test_vector_sim( SortUnitFL(), [ header_str,
# in in in in in out out out out out
# val [0] [1] [2] [3] val [0] [1] [2] [3]
[ 0, 0, 0, 0, 0, 0, x, x, x, x ],
[ 1, 4, 2, 3, 1, 0, x, x, x, x ],
[ 0, 0, 0, 0, 0, 1, 1, 2, 3, 4 ],
[ 0, 0, 0, 0, 0, 0, x, x, x, x ],
], dump_vcd )
def test_random(dump_vcd, test_verilog):
test_vector_table = [('in0', 'in1', 'min_*', 'max_*')]
for i in xrange(20):
in0 = Bits(8, randint(0, 0xff))
in1 = Bits(8, randint(0, 0xff))
test_vector_table.append([in0, in1, min(in0, in1), max(in0, in1)])
run_test_vector_sim(MinMaxUnit(), test_vector_table, dump_vcd,
test_verilog)
def test_32b_x_4b_mult(i, fix):
run_test_vector_sim(TestHarness(fix), [
('a b result*'),
[0, 0, 0],
[2, 3, 6],
[4, 5, 20],
[3, 4, 12],
[10, 13, 130],
[8, 7, 56],
])
def test_basic( dump_vcd ):
run_test_vector_sim( WireToWire(), [
('in_ out*'),
[ 0b00, '?'],
[ 0b10, 0b10 ],
[ 0b01, 0b10 ],
[ 0b11, 0b11 ],
[ 0b11, 0b11 ],
[ 0b11, 0b11 ],
], dump_vcd )
def test_random( dump_vcd, test_verilog ):
test_vector_table = [( 'in0', 'in1', 'min_*', 'max_*' )]
for i in xrange(20):
in0 = Bits( 8, randint(0,0xff) )
in1 = Bits( 8, randint(0,0xff) )
test_vector_table.append( [ in0, in1, min(in0,in1), max(in0,in1) ] )
run_test_vector_sim( MinMaxUnit(), test_vector_table,
dump_vcd, test_verilog )
def test_alu_add( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 0, 0x00000000, '?', '?', '?' ],
[ 0x0ffaa660, 0x00012304, 0, 0x0ffbc964, '?', '?', '?' ],
#pos-neg
[ 0x00132050, 0xd6620040, 0, 0xd6752090, '?', '?', '?' ],
[ 0xfff0a440, 0x00004450, 0, 0xfff0e890, '?', '?', '?' ],
# neg-neg
[ 0xfeeeeaa3, 0xf4650000, 0, 0xf353eaa3, '?', '?', '?' ],
], dump_vcd, test_verilog )
def test_dups( dump_vcd ):
run_test_vector_sim( SortUnitFL(), [ header_str,
# in in in in in out out out out out
# val [0] [1] [2] [3] val [0] [1] [2] [3]
[ 0, 0, 0, 0, 0, 0, x, x, x, x ],
[ 1, 8, 8, 8, 2, 0, x, x, x, x ],
[ 1, 9, 3, 3, 9, 1, 2, 8, 8, 8 ],
[ 1, 1, 1, 1, 1, 1, 3, 3, 9, 9 ],
[ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1 ],
[ 0, 0, 0, 0, 0, 0, x, x, x, x ],
], dump_vcd )
def test_stream( dump_vcd ):
run_test_vector_sim( SortUnitFL(), [ header_str,
# in in in in in out out out out out
# val [0] [1] [2] [3] val [0] [1] [2] [3]
[ 0, 0, 0, 0, 0, 0, x, x, x, x ],
[ 1, 2, 8, 9, 3, 0, x, x, x, x ],
[ 1, 9, 3, 4, 5, 1, 2, 3, 8, 9 ],
[ 1, 4, 7, 3, 8, 1, 3, 4, 5, 9 ],
[ 0, 0, 0, 0, 0, 1, 3, 4, 7, 8 ],
[ 0, 0, 0, 0, 0, 0, x, x, x, x ],
], dump_vcd )
def test_random(dump_vcd):
input_list = []
for i in range(15):
input_list.append(int(i * 16))
vec_table = []
vec_table.append(('in_', 'out*'))
vec_table.append([input_list[0], '?'])
for i in range(1, 15):
vec_table.append([input_list[i], input_list[i - 1] + 1])
print(vec_table)
run_test_vector_sim(RegIncr(), vec_table, dump_vcd)
def test_random(dump_vcd):
test_vector_table = [('in_', 'out*')]
last_result_0 = '?'
last_result_1 = '?'
for i in xrange(20):
rand_value = Bits(8, random.randint(0, 0xff))
test_vector_table.append([rand_value, last_result_1])
last_result_1 = last_result_0
last_result_0 = Bits(8, rand_value + 2)
run_test_vector_sim(RegIncr2stage(), test_vector_table, dump_vcd)
def test_random( dump_vcd ):
test_vector_table = [( 'in_', 'out*' )]
last_result_0 = '?'
last_result_1 = '?'
for i in xrange(20):
rand_value = Bits( 8, random.randint(0,0xff) )
test_vector_table.append( [ rand_value, last_result_1 ] )
last_result_1 = last_result_0
last_result_0 = Bits( 8, rand_value + 2 )
run_test_vector_sim( RegIncr2stage(), test_vector_table, dump_vcd )
def test_alu_sub( dump_vcd, test_verilog ):
run_test_vector_sim( AluRTL(), [
('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*'),
[ 0x00000000, 0x00000000, 1, 0x00000000, '?', '?', '?' ],
[ 0x0ffaa660, 0x00012304, 1, 0x0ff9835c, '?', '?', '?' ],
#pos-neg
[ 0x00000001, 0xffffffff, 1, 0x00000002, '?', '?', '?' ],
#neg-pos
[ 0xffff8000, 0x7fffffff, 1, 0x7fff8001, '?', '?', '?' ],
[ 0xfff0a440, 0x00004450, 1, 0xfff05ff0, '?', '?', '?' ],
# neg-neg
[ 0xfeeeeaa3, 0xf4650000, 1, 0x0a89eaa3, '?', '?', '?' ],
], dump_vcd, test_verilog )
def test_basic(dump_vcd):
run_test_vector_sim(
SortUnitFL(),
[
header_str,
# in in in in in out out out out out
# val [0] [1] [2] [3] val [0] [1] [2] [3]
[0, 0, 0, 0, 0, 0, x, x, x, x],
[1, 4, 2, 3, 1, 0, x, x, x, x],
[0, 0, 0, 0, 0, 1, 1, 2, 3, 4],
[0, 0, 0, 0, 0, 0, x, x, x, x],
],
dump_vcd)
def test():
run_test_vector_sim( ShamtGenPRTL(), [
('a shamt*'),
[0b11011, 1],
[0b11000, 4],
[0b00000, 32],
[0b00110, 2],
[0b10101, 1],
[0b00000, 32],
[0b11111, 1],
[0x40000000, 31],
[0x40000000, 31],
] )
def test_basic(dump_vcd, test_verilog):
run_test_vector_sim(
MinMaxUnit(),
[
header_str,
# in in out out
# in0 in1 out_min out_max
[0, 0, 0, 0],
[1, 4, 1, 4],
[3, 2, 2, 3],
[0, 0, 0, 0],
],
dump_vcd,
test_verilog)
def test_random(dump_vcd):
test_vector_table = [('in0', 'in1', 'in2', 'in3', 'out*')]
for i in xrange(100):
in0 = Bits(32, random.randint(0, 0xffffffff))
in1 = Bits(32, random.randint(0, 0xffffffff))
in2 = Bits(32, random.randint(0, 0xffffffff))
in3 = Bits(32, random.randint(0, 0xffffffff))
out = Bits(32, in0 + in1 + in2 + in3, trunc=True)
test_vector_table.append([in0, in1, in2, in3, out])
run_test_vector_sim(ReducerVRTL(), test_vector_table, dump_vcd)
def test_random( dump_vcd ):
test_vector_table = [( 'in0', 'in1', 'in2', 'in3', 'out*' )]
for i in xrange( 100 ):
in0 = Bits( 32, random.randint(0, 0xffffffff) )
in1 = Bits( 32, random.randint(0, 0xffffffff) )
in2 = Bits( 32, random.randint(0, 0xffffffff) )
in3 = Bits( 32, random.randint(0, 0xffffffff) )
out = Bits( 32, in0 + in1 + in2 + in3, trunc=True )
test_vector_table.append( [ in0, in1, in2, in3, out ] )
run_test_vector_sim( ReducerVRTL(), test_vector_table, dump_vcd )
def test_random( dump_vcd ):
test_vector_table = [ header_str,
# in in in in in out out out out out
# val [0] [1] [2] [3] val [0] [1] [2] [3]
[ 0, 0, 0, 0, 0, 0, x, x, x, x ],
[ 1, 0, 0, 0, 0, 0, x, x, x, x ],
]
last_results = [ 0, 0, 0, 0 ]
for i in xrange(20):
inputs = [ randint(0,0xff) for i in xrange(4) ]
test_vector_table.append( [1] + inputs + [1] + last_results )
last_results = deepcopy( sorted(inputs) )
run_test_vector_sim( SortUnitFL(), test_vector_table, dump_vcd )
def test_random( dump_vcd ):
test_vector_table = [( 'r_0', 'g_0', 'r_1', 'g_1', 'out*' )]
# first cycle outputs
out = Bits( 32, 0x0 )
for i in xrange( 100 ):
r_0 = Bits( 32, random.randint(0, 0xffffffff) )
g_0 = Bits( 32, random.randint(0, 0xffffffff) )
r_1 = Bits( 32, random.randint(0, 0xffffffff) )
g_1 = Bits( 32, random.randint(0, 0xffffffff) )
test_vector_table.append( [ r_0, g_0, r_1, g_1, out ] )
out = Bits( 32, r_0 * g_0 + r_1 * g_1, trunc=True )
run_test_vector_sim( MapperVRTL(), test_vector_table, dump_vcd )
def test_small( dump_vcd ):
run_test_vector_sim( MapperVRTL(), [
( 'r_0', 'g_0', 'r_1', 'g_1', 'out' ),
[ 0x01, 0x02, 0x03, 0x04, 0x00 ],
[ 0x03, 0x02, 0x03, 0x04, 0x0e ],
], dump_vcd )
def test_sorted( dump_vcd, test_verilog ):
run_test_vector_sim( SortUnitFlatRTL(), mk_test_vector_table( 3, [
[ 1, 2, 3, 4 ], [ 1, 3, 5, 7 ], [ 4, 3, 2, 1 ]
]), dump_vcd, test_verilog )
def test( test_params, dump_vcd ):
nstages = test_params.nstages
inputs = test_params.inputs
run_test_vector_sim( RegIncrNstage( nstages ),
mk_test_vector_table( nstages, inputs ), dump_vcd )
def test_stream( dump_vcd, test_verilog ):
run_test_vector_sim( SortUnitFlatRTL(), mk_test_vector_table( 3, [
[ 4, 3, 2, 1 ], [ 9, 6, 7, 1 ], [ 4, 8, 0, 9 ]
]), dump_vcd, test_verilog )
def test_random( dump_vcd, test_verilog ):
tvec_random = [ [ randint(0,0xff) for i in xr(4) ] for y in xr(20) ]
run_test_vector_sim( SortUnitFlatRTL(),
mk_test_vector_table( 3, tvec_random ), dump_vcd, test_verilog )
def test_custom(dump_vcd):
run_test_vector_sim(RegIncr(), [("in_ out*"), [0xAA, "?"], [0xBB, 0xAB], [0xAF, 0xBC], [0x00, 0xB0]], dump_vcd)
def test_random( n, dump_vcd ):
run_test_vector_sim( RegIncrNstage( nstages=n ),
mk_test_vector_table( n, sample(range(0xff),20) ), dump_vcd )
def test_overflow(dump_vcd):
run_test_vector_sim(RegIncr(), [("in_ out*"), [0x00, "?"], [0xFE, 0x01], [0xFF, 0xFF], [0x00, 0x00]], dump_vcd)
def test( test_params, dump_vcd ):
nstages = test_params.nstages
inputs = test_params.inputs
run_test_vector_sim( SortUnitCL( nstages=nstages ),
mk_test_vector_table( nstages, inputs ), dump_vcd )
def test_large(dump_vcd):
run_test_vector_sim(RegIncr(), [("in_ out*"), [0xA0, "?"], [0xB3, 0xA1], [0xC6, 0xB4], [0x00, 0xC7]], dump_vcd)
def test_small( dump_vcd ):
run_test_vector_sim( ReducerVRTL(), [
( 'in0', 'in1', 'in2', 'in3', 'out' ),
[ 0x01, 0x02, 0x03, 0x04, 0x0e ],
[ 0x03, 0x02, 0x03, 0x04, 0x11 ],
], dump_vcd )
def test_random( n, dump_vcd ):
tvec_random = [ [ randint(0,0xff) for i in xr(4) ] for y in xr(20) ]
run_test_vector_sim( SortUnitCL( nstages=n ),
mk_test_vector_table( n, tvec_random ), dump_vcd )
def test_dups( dump_vcd, test_verilog ):
run_test_vector_sim( SortUnitFlatRTL(), mk_test_vector_table( 3, [
[ 2, 8, 9, 9 ], [ 2, 8, 2, 8 ], [ 1, 1, 1, 1 ]
]), dump_vcd, test_verilog )
