def get_components_versions(self, libraryname, componentname):
""" list component version name in archive
"""
filelist = sy.list_files(self.library.library_path(libraryname) +
"/" + componentname)
outlist = []
for name in filelist:
# take only xml file
ext = XMLEXT[1:] # suppress dot
pattern = ".*%s" % ext + "$"
if re.match(pattern, name):
# Suppress extension
name = name.split(".")[0]
outlist.append(name)
return outlist
def get_components_versions(self, libraryname, componentname):
""" list component version name in archive
"""
filelist = sy.list_files(
self.library.library_path(libraryname) + "/" + componentname)
outlist = []
for name in filelist:
# take only xml file
ext = XMLEXT[1:] # suppress dot
pattern = ".*%s" % ext + "$"
if re.match(pattern, name):
# Suppress extension
name = name.split(".")[0]
outlist.append(name)
return outlist
def generate_tcl(self, filename=None):
""" generate tcl script
"""
if filename is None:
filename = self.project.name + TCLEXT
tclfile = open(
self.project.projectpath + SYNTHESISPATH + "/" + filename, "w")
tclfile.write("# TCL script automaticaly generated by POD\n")
# create project
tclfile.write("cd .." + OBJSPATH + "\n")
tclfile.write(self.project_base_creation())
# Configuration
tclfile.write("# configure platform params\n")
tclfile.write(self.project_base_configuration())
# Source files
tclfile.write("## add components sources file\n")
tclfile.write("# add top level sources file\n")
tclfile.write(
self.add_file_to_tcl(".." + SYNTHESISPATH + "/top_" +
self.project.name + VHDLEXT))
for directory in sy.list_dir(self.project.projectpath + SYNTHESISPATH):
for afile in sy.list_files(self.project.projectpath +
SYNTHESISPATH + "/" + directory):
tclfile.write(
self.add_file_to_tcl(".." + SYNTHESISPATH + "/" +
directory + "/" + afile))
# Constraints files
tclfile.write("# add constraint file\n")
tclfile.write(
self.add_constraints_file(SYNTHESISPATH + "/" + self.project.name))
tclfile.write(self.insert_tools_specific_commands())
tclfile.write(self.insert_tools_gen_cmds())
DISPLAY.msg("TCL script generated with name : " + self.project.name +
TCLEXT)
self.tcl_scriptname = self.project.name + TCLEXT
return self.tcl_scriptname
def generate_tcl(self, filename=None):
""" generate tcl script
"""
if filename is None:
filename = self.project.name + TCLEXT
tclfile = open(self.project.projectpath + SYNTHESISPATH + "/" +
filename, "w")
tclfile.write("# TCL script automaticaly generated by POD\n")
# create project
tclfile.write("cd .." + OBJSPATH + "\n")
tclfile.write(self.project_base_creation())
# Configuration
tclfile.write("# configure platform params\n")
tclfile.write(self.project_base_configuration())
# Source files
tclfile.write("## add components sources file\n")
tclfile.write("# add top level sources file\n")
tclfile.write(self.add_file_to_tcl(".." + SYNTHESISPATH + "/top_" +
self.project.name + VHDLEXT))
for directory in sy.list_dir(self.project.projectpath + SYNTHESISPATH):
for afile in sy.list_files(self.project.projectpath +
SYNTHESISPATH + "/" + directory):
tclfile.write(self.add_file_to_tcl(".." + SYNTHESISPATH + "/" +
directory + "/" + afile))
# Constraints files
tclfile.write("# add constraint file\n")
tclfile.write(self.add_constraints_file(SYNTHESISPATH + "/" +
self.project.name))
tclfile.write(self.insert_tools_specific_commands())
tclfile.write(self.insert_tools_gen_cmds())
DISPLAY.msg("TCL script generated with name : " +
self.project.name + TCLEXT)
self.tcl_scriptname = self.project.name + TCLEXT
return self.tcl_scriptname
def listcompletion(self, listargs, subargl, subargt):
""" return a list of possibility using template:
[] optional argument
<> mandatory arguments
masterinstancename : give list of instances with master bus interface
slaveinstancename : give list of instances with slave bus interface
libraryname : give list of available libraries
componentname : give list of components available in library
(for projectcli)
componentversion : give list of components version available in component
genericname : give list of generic instance name
platformlib : give list of platform library available
platformname : give list of platform available
instancename : give list of instances in project
interfacename : give list of interface in instance
portname : give list of port in interface
pinnum : give list of num for a port
simulationtoolchain: give list of toolchain available for simulation
drivertoolchain : give list of toolchain available for driver
synthesistoolchain : give list of toolchain available for synthesis
forcename : give list of pin where value can be forced
IO_name : give list of platform IO pin name
fpga_attributes : give list of fpga attributes in platform
"""
# read listargs (come from template)
if len(listargs) > 0:
if (
listargs[0][0] == "masterinstancename"
or listargs[0][0] == "slaveinstancename"
or listargs[0][0] == "instancename"
):
instance = self._project.get_instance(listargs[0][1])
instancename = instance.instancename
elif listargs[0][0] == "platformlib":
platformlib = listargs[0][1]
elif listargs[0][0] == "libraryname":
libraryname = listargs[0][1]
elif listargs[0][0] == "componentname":
componentname = listargs[0][1]
else:
return []
if len(listargs) > 1:
if listargs[1][0] == "interfacename":
interface = instance.get_interface(listargs[1][1])
interfacename = interface.name
elif listargs[1][0] == "componentname":
componentname = listargs[1][1]
else:
return []
if len(listargs) > 2:
if listargs[2][0] == "portname":
port = interface = interface.get_port(listargs[2][1])
portname = port.name
else:
return []
# fill list
if subargt == "masterinstancename":
return [interface.parent.instancename for interface in self._project.interfaces_master]
elif subargt == "slaveinstancename":
return [interface.parent.instancename for interface in self._project.interfaces_slave]
elif subargt == "instancename":
return [instance.instancename for instance in self._project.instances]
elif subargt == "interfacename":
return ["" + instancename + "." + interface.name for interface in instance.interfaces]
elif subargt == "masterinterfacename":
return ["" + instancename + "." + interface.name for interface in instance.master_interfaces]
elif subargt == "slaveinterfacename":
return ["" + instancename + "." + interface.name for interface in instance.slave_interfaces]
elif subargt == "portname":
return ["" + instancename + "." + interfacename + "." + port.name for port in interface.ports]
elif subargt == "pinnum":
return [
"" + instancename + "." + interfacename + "." + portname + "." + str(i) for i in range(int(port.size))
]
elif subargt == "libraryname":
arglist = self._project.library.libraries
return arglist
elif subargt == "platformlib":
arglist = SETTINGS.personal_platformlib_name_list
arglist.append("standard")
return arglist
elif subargt == "forcename":
arglist = ["" + port.name for port in self._project.platform.platform_ports]
return arglist
elif subargt == "forcestate":
return ["gnd", "vcc", "undef"]
elif subargt == "componentname":
try:
libraryname.lower()
except Exception as error:
raise error
arglist = [
libraryname + "." + componentname
for componentname in self._project.library.list_components(libraryname)
]
return arglist
elif subargt == "componentversion":
try:
libraryname.lower()
except Exception as error:
raise error
return [
libraryname + "." + componentname + "." + comp
for comp in self._project.get_components_versions(libraryname, componentname)
]
elif subargt == "platformname":
if platformlib == "standard":
return ["standard." + name for name in self._project.availables_plat()]
else:
return [platformlib + "." + name for name in sy.list_files(SETTINGS.get_platform_lib_path(platformlib))]
elif subargt == "genericname":
return ["" + instancename + "." + generic.name for generic in instance.generics]
elif subargt == "simulationtoolchain":
return self._project.get_simulation_toolchains()
elif subargt == "synthesistoolchain":
return self._project.get_synthesis_toolchains()
elif subargt == "drivertoolchain":
return self._project.get_driver_toolchains()
elif subargt == "IO_name":
return [port.name for port in self._project.get_ios()]
elif subargt == "fpga_attributes":
platform = self._project.platform
return platform.get_attr_names("fpga")
else:
return []
def listcompletion(self, listargs, subargl, subargt):
""" return a list of possibility using template:
[] optional argument
<> mandatory arguments
masterinstancename : give list of instances with master bus interface
slaveinstancename : give list of instances with slave bus interface
libraryname : give list of available libraries
componentname : give list of components available in library
(for projectcli)
componentversion : give list of components version available in component
genericname : give list of generic instance name
platformlib : give list of platform library available
platformname : give list of platform available
instancename : give list of instances in project
interfacename : give list of interface in instance
portname : give list of port in interface
pinnum : give list of num for a port
simulationtoolchain: give list of toolchain available for simulation
drivertoolchain : give list of toolchain available for driver
synthesistoolchain : give list of toolchain available for synthesis
forcename : give list of pin where value can be forced
IO_name : give list of platform IO pin name
fpga_attributes : give list of fpga attributes in platform
"""
# read listargs (come from template)
if len(listargs) > 0:
if listargs[0][0] == "masterinstancename" or\
listargs[0][0] == "slaveinstancename" or\
listargs[0][0] == "instancename":
instance = self._project.get_instance(listargs[0][1])
instancename = instance.instancename
elif listargs[0][0] == "platformlib":
platformlib = listargs[0][1]
elif listargs[0][0] == "libraryname":
libraryname = listargs[0][1]
elif listargs[0][0] == "componentname":
componentname = listargs[0][1]
else:
return []
if len(listargs) > 1:
if listargs[1][0] == "interfacename":
interface = instance.get_interface(listargs[1][1])
interfacename = interface.name
elif listargs[1][0] == "componentname":
componentname = listargs[1][1]
else:
return []
if len(listargs) > 2:
if listargs[2][0] == "portname":
port = interface = interface.get_port(listargs[2][1])
portname = port.name
else:
return []
# fill list
if subargt == "masterinstancename":
return [
interface.parent.instancename
for interface in self._project.interfaces_master
]
elif subargt == "slaveinstancename":
return [
interface.parent.instancename
for interface in self._project.interfaces_slave
]
elif subargt == "instancename":
return [
instance.instancename for instance in self._project.instances
]
elif subargt == "interfacename":
return [
"" + instancename + "." + interface.name
for interface in instance.interfaces
]
elif subargt == "masterinterfacename":
return [
"" + instancename + "." + interface.name
for interface in instance.master_interfaces
]
elif subargt == "slaveinterfacename":
return [
"" + instancename + "." + interface.name
for interface in instance.slave_interfaces
]
elif subargt == "portname":
return [
"" + instancename + "." + interfacename + "." + port.name
for port in interface.ports
]
elif subargt == "pinnum":
return [
"" + instancename + "." + interfacename + "." + portname +
"." + str(i) for i in range(int(port.size))
]
elif subargt == "libraryname":
arglist = self._project.library.libraries
return arglist
elif subargt == "platformlib":
arglist = SETTINGS.personal_platformlib_name_list
arglist.append("standard")
return arglist
elif subargt == "forcename":
arglist = [
"" + port.name
for port in self._project.platform.platform_ports
]
return arglist
elif subargt == "forcestate":
return ["gnd", "vcc", "undef"]
elif subargt == "componentname":
try:
libraryname.lower()
except Exception as error:
raise error
arglist = [
libraryname + "." + componentname for componentname in
self._project.library.list_components(libraryname)
]
return arglist
elif subargt == "componentversion":
try:
libraryname.lower()
except Exception as error:
raise error
return [
libraryname + "." + componentname + "." + comp
for comp in self._project.get_components_versions(
libraryname, componentname)
]
elif subargt == "platformname":
if platformlib == "standard":
return [
"standard." + name
for name in self._project.availables_plat()
]
else:
return [
platformlib + "." + name for name in sy.list_files(
SETTINGS.get_platform_lib_path(platformlib))
]
elif subargt == "genericname":
return [
"" + instancename + "." + generic.name
for generic in instance.generics
]
elif subargt == "simulationtoolchain":
return self._project.get_simulation_toolchains()
elif subargt == "synthesistoolchain":
return self._project.get_synthesis_toolchains()
elif subargt == "drivertoolchain":
return self._project.get_driver_toolchains()
elif subargt == "IO_name":
return [port.name for port in self._project.get_ios()]
elif subargt == "fpga_attributes":
platform = self._project.platform
return platform.get_attr_names("fpga")
else:
return []