def wrapFunctions(self):
#TODO: hardcoded name
self.addr_decoder_template = load_template('registers.vhdl')
self.designer.add_file(gen_path, "vhdl_wrapper.vhdl")
self.out = open(os.path.join(gen_path, 'vhdl', 'vhdl_wrapper.vhdl'),
'w')
for line in self.addr_decoder_template:
if '%%%INTERFACES%%%' in line:
self.printInterfaces()
elif '%%%MEMMAP%%%' in line:
self.printMemoryMap()
elif '%%%COMPONENTS%%%' in line:
self.printComponents()
elif '%%%SIGNALS%%%' in line:
self.printSignals()
elif '%%%RESET%%%' in line:
self.printReset()
elif '%%%RESET_RESULT_READY%%%' in line:
self.printResetResultReadyFlags()
elif '%%%RESULT_READY%%%' in line:
self.printResultReadyFlags()
elif '%%%RESET_INPUT_READY%%%' in line:
self.printResetInputReadyFlags()
elif '%%%READ_REGS%%%' in line:
self.printReadRegs()
elif '%%%WRITE_REGS%%%' in line:
self.printWriteRegs()
else:
print >> self.out, line,
self.out.close()
def write(self, test_vectors):
#TODO: hardcoded name
self.tb_template = load_template('tb.vhdl')
self.designer.add_file(gen_path, "tb.vhdl", synth=False)
self.out = open(os.path.join(gen_path, 'vhdl', 'tb.vhdl'), 'w' )
for line in self.tb_template:
if '%%%SIGNALS%%%' in line:
self.printSignals(test_vectors)
elif '%%%STIMULATE%%%' in line:
self.printTb(test_vectors)
else:
print >> self.out, line,
self.out.close()
def generate(self):
#TODO: hardcoded name
self.vhdl_main_template = load_template('poroto.vhdl')
self.designer.add_file(gen_path, "poroto.vhdl")
self.out = open(os.path.join(gen_path, 'vhdl', 'poroto.vhdl'), 'w')
for line in self.vhdl_main_template:
if '%%%MEMORY%%%' in line:
self.printMemoryMap()
elif '%%%MEM_COMPONENTS%%%' in line:
self.printMemoryComponents()
else:
print >> self.out, line,
self.out.close()
def generate(self):
#TODO: hardcoded name
self.vhdl_main_pkg_template = load_template('poroto_pkg.vhdl')
self.designer.add_file(gen_path, "poroto_pkg.vhdl")
self.out = open(os.path.join(gen_path, 'vhdl', 'poroto_pkg.vhdl'), 'w')
brams_nb = len(self.mem_map.mems)
#Temporary workaround
if brams_nb == 0:
brams_nb = 1
for line in self.vhdl_main_pkg_template:
if '%%%BRAMS_NB%%%' in line:
line = string.replace(line, '%%%BRAMS_NB%%%', str(brams_nb))
print >> self.out, line,
self.out.close()
def write(self, test_vectors):
self.designer.add_file(src_path, "StreamHandler.vhdl", synth=False)
#TODO: hardcoded name
self.tb_template = load_template('tb.vhdl')
self.designer.add_file(gen_path, "tb.vhdl", synth=False)
self.out = open(os.path.join(gen_path, 'vhdl', 'tb.vhdl'), 'w')
for line in self.tb_template:
if '%%%COMPONENTS%%%' in line:
self.printComponents(test_vectors)
elif '%%%SIGNALS%%%' in line:
self.printSignals(test_vectors)
elif '%%%PORTMAPS%%%' in line:
self.printPortMaps(test_vectors)
elif '%%%MEMORY%%%' in line:
self.printMemoryMap()
elif '%%%MEM_COMPONENTS%%%' in line:
self.printMemoryComponents()
elif '%%%STIMULATE%%%' in line:
self.printStimulate(test_vectors)
elif '%%%VERIFY%%%' in line:
self.printVerify(test_vectors)
else:
print >> self.out, line,
self.out.close()
def __init__(self, template_file):
self.template_file = template_file
self.clear_keys()
self.template = load_template(self.template_file)