parser.add_argument('-m',
'--model',
type=str,
nargs='+',
dest="model",
help="Source file(s) for behavioral model")
parser.add_argument(
'--model_top',
type=str,
help=
"Top-level module name of the behavioral model. Required if the model comprises multiple files/modules"
)
parser.add_argument(
'--model_parameters',
type=str,
nargs="+",
default=[],
help=
"Parameters for the behavioral model: PARAMETER0=VALUE0 PARAMETER1=VALUE1 ..."
)
args = parser.parse_args()
context = ArchitectureContext.unpickle(args.context)
model_top = find_verilog_top(args.model, args.model_top)
model_top.parameters = parse_parameters(args.model_parameters)
ostream = sys.stdout if args.output is None else args.output
generate_yosys_script(ostream, args.model, model_top,
context._yosys_script)
help="Source file(s) for the target design")
parser.add_argument('--model_top', type=str,
help="Top-level module name of the target design. Required if the design comprises multiple files/modules")
parser.add_argument('--model_includes', type=str, nargs="+", default=[],
help="Include directories for the target design")
parser.add_argument('--model_defines', type=str, nargs="+", default=[],
help="Macros for the target design. Use MACRO for valueless macro, and MACRO=VALUE for macros with value")
parser.add_argument('-c', '--compiler', type=str, choices=['vcs', 'iverilog'], dest='compiler', default="vcs",
help="Verilog compiler used to build the simulator")
args = parser.parse_args()
context = ArchitectureContext.unpickle(args.context)
channel_width = 2 * sum(sgmt.width * sgmt.length for sgmt in itervalues(context.segments))
# get verilog template
env = jj.Environment(loader=jj.FileSystemLoader(
os.path.join(os.path.abspath(os.path.dirname(__file__)), 'templates')))
tb_top = find_verilog_top(args.testbench, args.testbench_top)
behav_top = find_verilog_top(args.model, args.model_top)
ostream = sys.stdout if args.output is None else args.output
generate_makefile(args.context, env.get_template('tmpl.Makefile'), ostream,
tb_top, args.testbench, behav_top, args.model, context._yosys_script,
channel_width, context._vpr_archdef, context._vpr_rrgraph,
args.io_binding, context._verilog_sources, args.testbench_wrapper,
args.compiler, args.testbench_plus_args,
args.testbench_includes, args.testbench_defines, args.model_includes, args.model_defines)
processed[bit_name] = io
return processed
if __name__ == "__main__":
import argparse
parser = argparse.ArgumentParser(
description="IO assignment generator")
parser.add_argument('context', type=argparse.FileType(OpenMode.rb),
help="Pickled architecture context object")
parser.add_argument('-o', '--output', type=str, dest="output",
help="Generated IO assignments")
parser.add_argument('-m', '--model', type=str, nargs='+', dest="model",
help="Source file(s) for behavioral model")
parser.add_argument('--model_top', type=str,
help="Top-level module name of the behavioral model. Required if the model comprises multiple files/modules")
parser.add_argument('-f', '--fix', type=str, dest="fixed",
help="Partial assignments")
args = parser.parse_args()
enable_stdout_logging(__name__, logging.INFO)
context = ArchitectureContext.unpickle(args.context)
_logger.info("Architecture context parsed")
assignments = iobind(context, find_verilog_top(args.model, args.model_top),
parse_io_bindings(args.fixed) if args.fixed is not None else {})
# print results
ostream = sys.stdout if args.output is None else open(args.output, 'w')
for name, (x, y, subblock) in iteritems(assignments):
ostream.write("{} {} {} {}\n".format(name, x, y, subblock))
_logger.info("Assignment generated. Bye")