class BasicRtlSimulatorVcd(BasicRtlSimulatorWithSignalRegisterMethods):
supported_type_classes = (Bits, HEnum, Bits3t, Enum3t)
def create_wave_writer(self, file_name):
self.wave_writer = VcdWriter(open(file_name, "w"))
self.logChange = self._logChange
def finalize(self):
# because set_trace_file() may not be called
# and it this case the vcd config is not set
if self.wave_writer is None:
return
f = self.wave_writer._oFile
if f not in (sys.__stderr__, sys.__stdin__, sys.__stdout__):
f.close()
def _logChange(self, nowTime: int,
sig: BasicRtlSimProxy,
nextVal: HValue,
valueUpdater: Union[ValueUpdater, ArrayValueUpdater]):
"""
This method is called for every value change of any signal.
"""
try:
self.wave_writer.logChange(nowTime, sig, nextVal, valueUpdater)
except KeyError:
# not every signal has to be registered
# (if it is not registered it means it is ignored)
pass
def test_rewrite_AxiRegTC_test_write(self):
fIn = os.path.join(BASE, "AxiRegTC_test_write.vcd")
with open(fIn) as vcd_file:
vcd_in = VcdParser()
vcd_in.parse(vcd_file)
out = StringIO()
vcd_out = VcdWriter(out)
d = datetime.strptime("2018-03-21 20:20:48.479224",
"%Y-%m-%d %H:%M:%S.%f")
vcd_out.date(d)
vcd_out.timescale(1)
copy_signals_from_parser(vcd_in, vcd_out)
# for value writing we need to have it time order because
# we can not move back in time in VCD
all_updates = {}
aggregate_signal_updates_by_time(vcd_in.scope, all_updates)
for t, updates in sorted(all_updates.items()):
for sig, val in updates:
vcd_out.logChange(t, sig, val, None)
new_vcd_str = out.getvalue()
# parse it again to check if format is correct
vcd_in = VcdParser()
vcd_in.parse_str(new_vcd_str)
def set_trace_file(self, file_name, trace_depth):
vcd = self.wave_writer = VcdWriter(open(file_name, "w"))
vcd.date(datetime.now())
vcd.timescale(1)
interface_signals = set()
self._collect_interface_signals(self.synthesised_unit, self.model,
interface_signals)
self.wave_register_signals(self.synthesised_unit, self.model, None,
interface_signals)
vcd.enddefinitions()
def test_example0(self):
out = StringIO()
vcd = VcdWriter(out)
d = datetime.strptime("2018-04-12 18:04:03.652880",
"%Y-%m-%d %H:%M:%S.%f")
vcd.date(d)
vcd.timescale(1)
example_dump_values0(vcd)
with open(os.path.join(BASE, "example0.vcd")) as f:
ref = f.read()
out = out.getvalue()
self.assertEqual(ref, out)
def test_example0(self):
class MaskedValue():
def __init__(self, val, vld_mask):
self.val = val
self.vld_mask = vld_mask
out = StringIO()
vcd = VcdWriter(out)
d = datetime.strptime("2018-04-12 18:04:03.652880",
"%Y-%m-%d %H:%M:%S.%f")
vcd.date(d)
vcd.timescale(1)
sig0 = "sig0"
vect0 = "vect0"
sig1 = "sig1"
with vcd.varScope("unit0") as m:
m.addVar(sig0, sig0, VCD_SIG_TYPE.WIRE, 1, VcdBitsFormatter())
m.addVar(sig1, sig1, VCD_SIG_TYPE.WIRE, 1, VcdBitsFormatter())
m.addVar(vect0, vect0, VCD_SIG_TYPE.WIRE, 16, VcdBitsFormatter())
vcd.enddefinitions()
for s in [sig0, sig1, vect0]:
vcd.logChange(0, s, MaskedValue(0, 0), None)
vcd.logChange(1, sig0, MaskedValue(0, 1), None)
vcd.logChange(2, sig1, MaskedValue(1, 1), None)
vcd.logChange(3, vect0, MaskedValue(10, (1 << 16) - 1), None)
vcd.logChange(4, vect0, MaskedValue(20, (1 << 16) - 1), None)
with open(os.path.join(BASE, "example0.vcd")) as f:
ref = f.read()
out = out.getvalue()
self.assertEqual(ref, out)
def __init__(self, dumpFile=sys.stdout):
self.vcdWriter = VcdWriter(dumpFile)
self.logPropagation = False
self.logApplyingValues = False
self._obj2scope = {}
self._traced_signals = set()
class BasicRtlSimConfigVcd(BasicRtlSimConfig):
supported_type_classes = (Bits, HEnum, Bits3t, Enum3t)
def __init__(self, dumpFile=sys.stdout):
self.vcdWriter = VcdWriter(dumpFile)
self.logPropagation = False
self.logApplyingValues = False
self._obj2scope = {}
self._traced_signals = set()
def collectInterfaceSignals(self, obj: Union[Interface, Unit],
model: BasicRtlSimModel,
res: Set[BasicRtlSimProxy]):
if hasattr(obj, "_interfaces") and obj._interfaces:
for chIntf in obj._interfaces:
self.collectInterfaceSignals(chIntf, model, res)
if isinstance(obj, Unit):
for u in obj._units:
m = getattr(model, u._name + "_inst")
if u._shared_component_with is not None:
u, _, _ = u._shared_component_with
self.collectInterfaceSignals(u, m, res)
else:
sig_name = obj._sigInside.name
s = getattr(model.io, sig_name)
res.add(s)
def vcdRegisterSignals(self, obj: Union[Interface,
Unit], model: BasicRtlSimModel,
parent: Optional[VcdVarWritingScope],
interface_signals: Set[BasicRtlSimProxy]):
"""
Register signals from interfaces for Interface or Unit instances
"""
if obj._interfaces:
if isinstance(obj, Unit):
name = model._name
else:
name = obj._name
parent_ = self.vcdWriter if parent is None else parent
subScope = parent_.varScope(name)
self._obj2scope[obj] = subScope
with subScope:
# register all subinterfaces
for chIntf in obj._interfaces:
self.vcdRegisterSignals(chIntf, model, subScope,
interface_signals)
if isinstance(obj, Unit):
self.vcdRegisterRemainingSignals(subScope, model,
interface_signals)
# register interfaces from all subunits
for u in obj._units:
m = getattr(model, u._name + "_inst")
if u._shared_component_with is not None:
u, _, _ = u._shared_component_with
self.vcdRegisterSignals(u, m, subScope,
interface_signals)
return subScope
else:
t = obj._dtype
if isinstance(t, self.supported_type_classes):
tName, width, formatter = vcdTypeInfoForHType(t)
sig_name = obj._sigInside.name
s = getattr(model.io, sig_name)
try:
parent.addVar(s, sig_name, tName, width, formatter)
except VarAlreadyRegistered:
pass
def vcdRegisterRemainingSignals(self, unitScope, model: BasicRtlSimModel,
interface_signals: Set[BasicRtlSimProxy]):
for s in model._interfaces:
if s not in interface_signals and s not in self.vcdWriter._idScope:
t = s._dtype
if isinstance(t, self.supported_type_classes):
tName, width, formatter = vcdTypeInfoForHType(t)
try:
unitScope.addVar(s, s._name, tName, width, formatter)
except VarAlreadyRegistered:
pass
def beforeSim(self, simulator: HdlSimulator, synthesisedUnit: Unit,
model: BasicRtlSimModel):
"""
This method is called before first step of simulation.
"""
vcd = self.vcdWriter
vcd.date(datetime.now())
vcd.timescale(1)
interface_signals = set()
self.collectInterfaceSignals(synthesisedUnit, model, interface_signals)
self.vcdRegisterSignals(synthesisedUnit, model, None,
interface_signals)
vcd.enddefinitions()
def logChange(self, nowTime: int, sig: BasicRtlSimProxy, nextVal):
"""
This method is called for every value change of any signal.
"""
try:
self.vcdWriter.logChange(nowTime, sig, nextVal)
except KeyError:
# not every signal has to be registered
# (if it is not registered it means it is ignored)
pass
def create_wave_writer(self, file_name):
self.wave_writer = VcdWriter(open(file_name, "w"))
def copy_signals_from_parser(vcd_in: VcdParser, vcd_out: VcdWriter):
root = list(vcd_in.scope.children.values())[0]
copy_signals_from_parser_recursion(root, vcd_out)
vcd_out.enddefinitions()
class VcdHdlSimConfig(HdlSimConfig):
supported_type_classes = (HBool, Bits, HEnum)
def __init__(self, dumpFile=sys.stdout):
self.vcdWriter = VcdWriter(dumpFile)
self.logPropagation = False
self.logApplyingValues = False
self._obj2scope = {}
def vcdRegisterInterfaces(self, obj: Union[Interface, Unit],
parent: Optional[VcdVarWritingScope]):
"""
Register signals from interfaces for Interface or Unit instances
"""
if hasattr(obj, "_interfaces") and obj._interfaces:
name = obj._name
parent_ = self.vcdWriter if parent is None else parent
subScope = parent_.varScope(name)
self._obj2scope[obj] = subScope
with subScope:
# register all subinterfaces
for chIntf in obj._interfaces:
self.vcdRegisterInterfaces(chIntf, subScope)
if isinstance(obj, (Unit, SimModel)):
# register interfaces from all subunits
for u in obj._units:
self.vcdRegisterInterfaces(u, subScope)
return subScope
else:
t = obj._dtype
if isinstance(t, self.supported_type_classes):
tName, width, formatter = vcdTypeInfoForHType(t)
try:
parent.addVar(obj, getSignalName(obj), tName, width,
formatter)
except VarAlreadyRegistered:
pass
def vcdRegisterRemainingSignals(self, unit: Union[Interface, Unit]):
unitScope = self._obj2scope[unit]
for s in unit._ctx.signals:
if s not in self.vcdWriter._idScope:
t = s._dtype
if isinstance(t, self.supported_type_classes):
tName, width, formatter = vcdTypeInfoForHType(t)
unitScope.addVar(s, getSignalName(s), tName, width,
formatter)
for u in unit._units:
self.vcdRegisterRemainingSignals(u)
def initUnitSignalsForInterfaces(self, unit):
self._scope = self.registerInterfaces(unit)
for s in unit._ctx.signals:
if s not in self.vcdWriter._idScope:
self.registerSignal(s)
for u in unit._units:
self.initUnitSignals(u)
def beforeSim(self, simulator, synthesisedUnit):
"""
This method is called before first step of simulation.
"""
vcd = self.vcdWriter
vcd.date(datetime.now())
vcd.timescale(1)
self.vcdRegisterInterfaces(synthesisedUnit, None)
self.vcdRegisterRemainingSignals(synthesisedUnit)
vcd.enddefinitions()
def logChange(self, nowTime, sig, nextVal):
"""
This method is called for every value change of any signal.
"""
try:
self.vcdWriter.logChange(nowTime, sig, nextVal)
except KeyError:
# not every signal has to be registered
pass
def create_wave_writer(self, file_name):
self.wave_writer = VcdWriter(open(file_name, "w"))
self.logChange = self._logChange
