def VLibFilter(gen):
"""A line based output stream filter for Riviera-PRO's VHDL library management tool."""
for line in gen:
if line.startswith("ALIB: Library "):
yield LogEntry(line, Severity.Verbose)
else:
yield LogEntry(line, Severity.Normal)
def CompilerFilter(gen):
for line in gen:
if line.startswith("ERROR "):
yield LogEntry(line, Severity.Error)
elif line.startswith("WARNING "):
yield LogEntry(line, Severity.Warning)
elif line.startswith("INFO "):
yield LogEntry(line, Severity.Info)
else:
yield LogEntry(line, Severity.Normal)
def VLibFilter(gen):
for line in gen:
if line.startswith("** Warning: "):
yield LogEntry(line, Severity.Warning)
elif line.startswith("** Error"):
yield LogEntry(line, Severity.Error)
elif line.startswith("** Fatal: "):
yield LogEntry(line, Severity.Error)
else:
yield LogEntry(line, Severity.Normal)
def CoreGeneratorFilter(gen):
for line in gen:
if line.startswith("ERROR:"):
yield LogEntry(line, Severity.Error)
elif line.startswith("WARNING:"):
yield LogEntry(line, Severity.Warning)
elif line.startswith("Note:"):
yield LogEntry(line, Severity.Info)
else:
yield LogEntry(line, Severity.Normal)
def PoCSimulationResultFilter(gen, simulationResult):
state = 0
for line in gen:
if ((state == 0) and
(line.Message == "========================================")):
state += 1
elif ((state == 1) and (line.Message == "POC TESTBENCH REPORT")):
state += 1
yield LogEntry(
"{COLOR}{line}{NOCOLOR}".format(
COLOR=Init.Foreground['DARK_CYAN'],
line=line.Message,
**Init.Foreground), line.Severity, line.Indent)
continue
elif ((state == 2) and
(line.Message == "========================================")):
state += 1
elif ((state == 3) and
(line.Message == "========================================")):
state += 1
elif ((state == 4)
and line.Message.startswith("SIMULATION RESULT = ")):
state += 1
if line.Message.endswith("FAILED"):
color = Init.Foreground['RED']
simulationResult <<= SimulationResult.Failed
elif line.Message.endswith("NO ASSERTS"):
color = Init.Foreground['YELLOW']
simulationResult <<= SimulationResult.NoAsserts
elif line.Message.endswith("PASSED"):
color = Init.Foreground['GREEN']
simulationResult <<= SimulationResult.Passed
else:
color = Init.Foreground['RED']
simulationResult <<= SimulationResult.Error
yield LogEntry(
"{COLOR}{line}{NOCOLOR}".format(COLOR=color,
line=line.Message,
**Init.Foreground),
line.Severity, line.Indent)
continue
elif ((state == 5) and
(line.Message == "========================================")):
state += 1
yield line
if (state != 6):
raise pyIPCMISimulationResultNotFoundException(
"No PoC Testbench Report in simulator output found.")
def XstFilter(gen):
flagNormal = False
for line in gen:
if line.startswith("ERROR:"):
yield LogEntry(line, Severity.Error)
elif line.startswith("WARNING:"):
yield LogEntry(line, Severity.Warning)
elif line.startswith("Note:"):
yield LogEntry(line, Severity.Info)
elif line.startswith("* "): # progress
yield LogEntry(line, Severity.Normal)
flagNormal = True
else:
yield LogEntry(line, Severity.Normal if flagNormal else Severity.Verbose)
flagNormal = False
def CocotbSimulationResultFilter(gen, simulationResult):
passedRegExpStr = r".*?in tear_down\s+Passed \d+ tests" # Source filename
passedRegExp = re_compile(passedRegExpStr)
failedRegExpStr = r".*?in tear_down\s+Failed \d+ out of \d+ tests" # Source filename
failedRegExp = re_compile(failedRegExpStr)
for line in gen:
color = None
passedRegExpMatch = passedRegExp.match(str(line))
failedRegExpMatch = failedRegExp.match(str(line))
if passedRegExpMatch is not None:
color = Init.Foreground['GREEN']
simulationResult <<= SimulationResult.Passed
elif failedRegExpMatch is not None:
color = Init.Foreground['RED']
simulationResult <<= SimulationResult.Failed
# color is set when message should be printed
if color is not None:
yield LogEntry(
"{COLOR}{line}{NOCOLOR}".format(COLOR=color,
line=line.Message,
**Init.Foreground),
line.Severity, line.Indent)
continue
yield line
def SimulatorFilter(gen):
for line in gen:
if line.startswith("ISim "):
yield LogEntry(line, Severity.Debug)
elif line.startswith("This is a Full version of ISim."):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Time resolution is "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Simulator is doing circuit initialization process."):
yield LogEntry(line, Severity.Debug)
elif line.startswith("Finished circuit initialization process."):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("ERROR:"):
yield LogEntry(line, Severity.Error)
elif line.startswith("WARNING:"):
yield LogEntry(line, Severity.Warning)
elif line.startswith("INFO:"):
yield LogEntry(line, Severity.Verbose)
else:
yield LogEntry(line, Severity.Normal)
def CompilerFilter(gen):
for line in gen:
if line.startswith("ERROR: "):
yield LogEntry(line, Severity.Error)
elif line.startswith("WARNING: "):
yield LogEntry(line, Severity.Warning)
elif line.startswith("INFO: "):
yield LogEntry(line, Severity.Info)
elif line.startswith("Start"):
yield LogEntry(line, Severity.Normal)
elif line.startswith("Finished"):
yield LogEntry(line, Severity.Normal)
elif line.startswith("****** Vivado "):
yield LogEntry(line, Severity.Debug)
elif line.startswith(" **** SW Build "):
yield LogEntry(line, Severity.Debug)
elif line.startswith(" **** IP Build "):
yield LogEntry(line, Severity.Debug)
elif line.startswith(" ** Copyright "):
continue
elif line.startswith("# "):
yield LogEntry(line, Severity.Debug)
else:
yield LogEntry(line, Severity.Verbose)
def GNUMakeQuestaSimFilter(gen):
for line in gen:
if line.startswith("# --"): yield LogEntry(line, Severity.Verbose)
elif line.startswith("# Loading"):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("# ** Note"):
yield LogEntry(line, Severity.Info)
elif line.startswith("# ** Warn"):
yield LogEntry(line, Severity.Warning)
elif line.startswith("# ** Erro"):
yield LogEntry(line, Severity.Error)
elif line.startswith("# ** Fata"):
yield LogEntry(line, Severity.Error)
elif line.startswith("# //"):
continue
else:
yield LogEntry(line, Severity.Normal)
def GTKWaveFilter(gen):
for line in gen:
yield LogEntry(line, Severity.Normal)
def SimulatorFilter(gen):
pyIPCMIOutputFound = False
for line in gen:
if (line == ""):
if (not pyIPCMIOutputFound):
continue
else:
yield LogEntry(line, Severity.Normal)
elif line.startswith("Vivado Simulator "):
continue
elif line.startswith("****** xsim "):
yield LogEntry(line, Severity.Debug)
elif line.startswith(" **** SW Build "):
yield LogEntry(line, Severity.Debug)
elif line.startswith(" **** IP Build "):
yield LogEntry(line, Severity.Debug)
elif line.startswith(" ** Copyright "):
continue
elif line.startswith("INFO: [Common 17-206] Exiting xsim "):
continue
elif line.startswith("source "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("# ") or line.startswith("## "):
yield LogEntry(line, Severity.Debug)
elif line.startswith("Time resolution is "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("========================================"):
pyIPCMIOutputFound = True
yield LogEntry(line, Severity.Normal)
elif line.startswith("Failure: "):
yield LogEntry(line, Severity.Error)
elif line.startswith("FATAL_ERROR: "):
yield LogEntry(line, Severity.Error)
else:
yield LogEntry(line, Severity.Normal)
def ElaborationFilter(gen): # mccabe:disable=MC0001
for line in gen:
if line.startswith("Vivado Simulator "):
continue
elif line.startswith("Copyright 1986-1999"):
continue
elif line.startswith("Running: "):
yield LogEntry(line, Severity.Debug)
elif line.startswith("ERROR: "):
yield LogEntry(line, Severity.Error)
elif line.startswith("WARNING: "):
yield LogEntry(line, Severity.Warning)
elif line.startswith("INFO: "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Multi-threading is "):
yield LogEntry(line, Severity.Debug)
elif line.startswith("Determining compilation order of HDL files."):
yield LogEntry(line, Severity.Debug)
elif line.startswith("Determining compilation order of HDL files."):
yield LogEntry(line, Severity.Debug)
elif line.startswith("Starting static elaboration"):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Completed static elaboration"):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Starting simulation data flow analysis"):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Completed simulation data flow analysis"):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Time Resolution for simulation is"):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Compiling package "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Compiling architecture "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Built simulation snapshot "):
yield LogEntry(line, Severity.Verbose)
elif ": warning:" in line:
yield LogEntry(line, Severity.Warning)
else:
yield LogEntry(line, Severity.Normal)
def VSimFilter(gen):
"""A line based output stream filter for Active-HDL's VHDL simulator."""
pyIPCMIOutputFound = False
for line in gen:
if line.startswith("asim"):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("VSIM: "):
yield LogEntry(line, Severity.Verbose)
elif (line.startswith("ELBREAD: Warning: ")
and line.endswith("not bound.")):
yield LogEntry(line, Severity.Error)
elif line.startswith("ELBREAD: Error: "):
yield LogEntry(line, Severity.Error)
elif line.startswith("ELBREAD: "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("ELAB2: "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("SLP: "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Allocation: "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith(
"KERNEL: ========================================"):
pyIPCMIOutputFound = True
yield LogEntry(line[8:], Severity.Normal)
elif line.startswith("KERNEL: "):
if (not pyIPCMIOutputFound):
yield LogEntry(line, Severity.Verbose)
else:
yield LogEntry(line[8:], Severity.Normal)
else:
yield LogEntry(line, Severity.Normal)
def VSimFilter(gen):
pyIPCMIOutputFound = False
for line in gen:
if line.startswith("# Loading "):
yield LogEntry(line, Severity.Debug)
elif line.startswith("# //"):
if line[6:].startswith("Questa"):
yield LogEntry(line, Severity.Debug)
elif line[6:].startswith("Version "):
yield LogEntry(line, Severity.Debug)
else:
continue
elif line.startswith("# ========================================"):
pyIPCMIOutputFound = True
yield LogEntry(line[2:], Severity.Normal)
elif line.startswith("# ** Warning: "):
yield LogEntry(line, Severity.Warning)
elif line.startswith("# ** Error"):
yield LogEntry(line, Severity.Error)
elif line.startswith("# ** Fatal: "):
yield LogEntry(line, Severity.Error)
elif line.startswith("** Fatal: "):
yield LogEntry(line, Severity.Error)
elif line.startswith("# %%"):
if ("ERROR" in line):
yield LogEntry(
"{DARK_RED}{line}{NOCOLOR}".format(line=line[2:],
**Init.Foreground),
Severity.Error)
else:
yield LogEntry(
"{DARK_CYAN}{line}{NOCOLOR}".format(line=line[2:],
**Init.Foreground),
Severity.Normal)
elif line.startswith("# "):
if (not pyIPCMIOutputFound):
yield LogEntry(line, Severity.Verbose)
else:
yield LogEntry(line[2:], Severity.Normal)
else:
yield LogEntry(line, Severity.Normal)
def VhCompFilter(gen): for line in gen: yield LogEntry(line, Severity.Normal)
def VComFilter(gen): # mccabe:disable=MC0001
"""A line based output stream filter for Active-HDL's VHDL compiler."""
for line in gen:
if line.startswith("Aldec, Inc. VHDL Compiler"):
yield LogEntry(line, Severity.Debug)
elif line.startswith("DAGGEN WARNING DAGGEN_0523"):
yield LogEntry(line, Severity.Debug)
elif line.startswith("ACOMP Initializing"):
yield LogEntry(line, Severity.Debug)
elif line.startswith("VLM Initialized with path"):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("VLM ERROR "):
yield LogEntry(line, Severity.Error)
elif line.startswith("COMP96 File: "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("COMP96 Compile Package "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("COMP96 Compile Entity "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("COMP96 Compile Architecture "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("COMP96 Compile success "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("COMP96 Compile failure "):
yield LogEntry(line, Severity.Error)
elif line.startswith("COMP96 WARNING "):
yield LogEntry(line, Severity.Warning)
elif line.startswith("ELAB1 WARNING ELAB1_0026:"):
yield LogEntry(line, Severity.Warning)
elif line.startswith("COMP96 ERROR "):
yield LogEntry(line, Severity.Error)
else:
yield LogEntry(line, Severity.Normal)
def FuseFilter(gen):
for line in gen:
if line.startswith("ISim "):
yield LogEntry(line, Severity.Debug)
elif line.startswith("Fuse "):
yield LogEntry(line, Severity.Debug)
elif line.startswith("Determining compilation order of HDL files"):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Parsing VHDL file "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("WARNING:HDLCompiler:"):
yield LogEntry(line, Severity.Warning)
elif line.startswith("Starting static elaboration"):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Completed static elaboration"):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Compiling package "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Compiling architecture "):
yield LogEntry(line, Severity.Verbose)
elif line.startswith("Time Resolution for simulation is"):
yield LogEntry(line, Severity.Verbose)
elif (line.startswith("Waiting for ") and line.endswith(" to finish...")):
yield LogEntry(line, Severity.Verbose)
elif (line.startswith("Compiled ") and line.endswith(" VHDL Units")):
yield LogEntry(line, Severity.Verbose)
else:
yield LogEntry(line, Severity.Normal)