def test_asuint(): basis_tester(asuint_basis_cases) encounter_error_tester(asuint_type_wrong_cases) encounter_error_tester(asuint_width_wrong_cases) serialize_equal(AsUInt(u(20, w(5)), uw(5)), 'asUInt(UInt<5>("h14"))') serialize_equal(AsUInt(s(-20, w(6)), uw(5)), 'asUInt(SInt<6>("h-14"))') serialize_equal(AsUInt(n("clock", ClockType()), uw(1)), 'asUInt(clock)')
def type_wrong_cases_1_arg_gen(op): wrong_cases = [ op_args(op, UnknownType).tpe(lambda x: uw(32)), op_args(op, VectorType).tpe(lambda x: uw(32)), op_args(op, BundleType).tpe(lambda x: uw(32)), ] return wrong_cases
def test_sub_access_non_vector(): sa = SubAccess(n("vc", uw(8)), u(2, w(3)), uw(8)) assert not check(sa) sa = SubAccess(n("vc", bdl(a=(vec(uw(8), 10), True))), u(2, w(3)), vec(uw(8), 10)) assert not check(sa)
def test_sub_field_type_wrong(): bd = bdl(a=(uw(8), False), b=(sw(8), False)) sf = SubField(n("bd", bd), "a", sw(8)) assert not check(sf) bd = bdl(a=(bdl(c=(uw(8), True)), False), b=(sw(8), False)) sf = SubField(n("bd", bd), "a", bdl(c=(uw(9), True))) assert not check(sf)
def test_sub_field_non_exist(): bd = bdl(a=(uw(8), False), b=(sw(8), False)) sf = SubField(n("bd", bd), "c", uw(8)) assert not check(sf) bd = bdl(a=(bdl(c=(uw(8), True)), False), b=(sw(8), False)) sf = SubField(n("bd", bd), "c", bdl(c=(uw(8), True))) assert not check(sf)
def test_sub_access_idx_non_uint(): vc = vec(uw(8), 10) sa = SubAccess(n("vc", vc), s(2, w(3)), uw(8)) assert not check(sa) vc = vec(uw(8), 10) sa = SubAccess(n("vc", vc), n("a", sw(8)), uw(8)) assert not check(sa)
def test_and(): basis_tester(and_basis_cases) encounter_error_tester(and_type_wrong_cases) encounter_error_tester(and_width_wrong_cases) serialize_equal(And([u(20, w(5)), u(15, w(4))], uw(5)), 'and(UInt<5>("h14"), UInt<4>("hf"))') serialize_equal(And([s(-20, w(6)), s(-15, w(5))], uw(6)), 'and(SInt<6>("h-14"), SInt<5>("h-f"))')
def test_write_port_clock_wrong(): mem_ref = n("m", vec(uw(8), 10)) mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", uw(1))) assert not check(mw) mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10)) mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), u(0, w(1))) assert not check(mw)
def test_memory_basis(): mem = DefMemory("m", vec(uw(8), 10)) assert check(mem) serialize_stmt_equal(mem, 'cmem m : UInt<8>[10]') mem = DefMemory("m", vec(bdl(a=(uw(8), False)), 10)) assert check(mem) serialize_stmt_equal(mem, 'cmem m : {a : UInt<8>}[10]')
def test_read_port_mem_wrong(): mem_ref = n("m", bdl(a=(vec(uw(8), 10), False))) mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", ClockType())) assert not check(mr) mem_ref = n("m", uw(9)) mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), n("clock", ClockType())) assert not check(mr)
def test_sub_index_over_bound(): vc = vec(uw(8), 10) si = SubIndex(n("vc", vc), 10, uw(8)) assert not check(si) vc = vec(vec(uw(8), 10), 20) si = SubIndex(n("vc", vc), -1, vec(uw(8), 10)) assert not check(si)
def test_dshr(): basis_tester(dshr_basis_cases) encounter_error_tester(dshr_type_wrong_cases) encounter_error_tester(dshr_width_wrong_cases) serialize_equal(Dshr([u(20, w(5)), u(15, w(4))], uw(5)), 'dshr(UInt<5>("h14"), UInt<4>("hf"))') serialize_equal(Dshr([s(-20, w(6)), u(15, w(4))], uw(6)), 'dshr(SInt<6>("h-14"), UInt<4>("hf"))')
def test_register_basis(): r1 = DefRegister("r1", uw(8), n("clock", ClockType())) assert check(r1) serialize_stmt_equal(r1, 'reg r1 : UInt<8>, clock') r2 = DefRegister("r2", vec(uw(8), 10), n("clock", ClockType())) assert check(r2) serialize_stmt_equal(r2, 'reg r2 : UInt<8>[10], clock')
def test_write_port_mem_wrong(): mem_ref = n("m", bdl(a=(vec(uw(8), 10), False))) mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", ClockType())) assert not check(mw) mem_ref = n("m", uw(9)) mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), n("clock", ClockType())) assert not check(mw)
def test_shr(): basis_tester(shr_basis_cases) encounter_error_tester(shr_type_wrong_cases) encounter_error_tester(shr_width_wrong_cases) serialize_equal(Shr(u(20, w(5)), 3, uw(2)), 'shr(UInt<5>("h14"), 3)') serialize_equal(Shr(s(-20, w(6)), 3, uw(3)), 'shr(SInt<6>("h-14"), 3)')
def test_cat(): basis_tester(cat_basis_cases) encounter_error_tester(cat_type_wrong_cases) encounter_error_tester(cat_width_wrong_cases) serialize_equal(Cat([u(20, w(5)), u(15, w(4))], uw(9)), 'cat(UInt<5>("h14"), UInt<4>("hf"))') serialize_equal(Cat([s(-20, w(6)), s(-15, w(5))], uw(11)), 'cat(SInt<6>("h-14"), SInt<5>("h-f"))')
def test_div(): basis_tester(div_basis_cases) encounter_error_tester(div_type_wrong_cases) encounter_error_tester(div_width_wrong_cases) serialize_equal(Div([u(20, w(5)), u(15, w(4))], uw(5)), 'div(UInt<5>("h14"), UInt<4>("hf"))') serialize_equal(Div([s(-20, w(6)), s(-15, w(5))], uw(7)), 'div(SInt<6>("h-14"), SInt<5>("h-f"))')
def test_leq(): basis_tester(leq_basis_cases) encounter_error_tester(leq_type_wrong_cases) encounter_error_tester(leq_width_wrong_cases) serialize_equal(Leq([u(20, w(5)), u(15, w(4))], uw(1)), 'leq(UInt<5>("h14"), UInt<4>("hf"))') serialize_equal(Leq([s(-20, w(6)), s(-15, w(5))], uw(1)), 'leq(SInt<6>("h-14"), SInt<5>("h-f"))')
def test_sub_index_type_wrong(): vc = vec(uw(8), 10) si = SubIndex(n("vc", vc), 5, sw(8)) assert not check(si) vc = vec(vec(uw(8), 10), 20) si = SubIndex(n("vc", vc), 19, vec(uw(8), 20)) assert not check(si)
def test_wire_basis(): wire = DefWire("w1", uw(8)) assert check(wire) serialize_stmt_equal(wire, 'wire w1 : UInt<8>') wire = DefWire("w2", bdl(a=(uw(8), True), b=(sw(8), False))) assert check(wire) serialize_stmt_equal(wire, 'wire w2 : {flip a : UInt<8>, b : SInt<8>}')
def test_init_register_clock_wrong(): r1 = DefInitRegister("r1", uw(8), n("clock", uw(1)), n("r", uw(1)), u(5, w(8))) assert not check(r1) r2 = DefInitRegister("r2", sw(8), n("clock", sw(1)), u(0, w(1)), s(5, w(8))) assert not check(r2)
def test_init_register_type_not_match(): r1 = DefInitRegister("r1", uw(8), n("clock", ClockType()), n("r", uw(1)), s(5, w(8))) assert not check(r1) r2 = DefInitRegister("r2", uw(8), n("clock", ClockType()), u(0, w(1)), s(5, w(8))) assert not check(r2)
def test_read_port_clock_wrong(): mem_ref = n("m", vec(uw(8), 10)) mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", uw(1))) assert not check(mr) mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10)) mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), u(0, w(1))) assert not check(mr)
def test_mux_basis(): mux = Mux(n("c", uw(1)), n("a", uw(8)), n("b", uw(8)), uw(8)) assert check(mux) serialize_equal(mux, "mux(c, a, b)") mux = Mux(u(1, w(1)), n("b", vec(sw(8), 10)), n("c", vec(sw(8), 10)), vec(sw(8), 10)) assert check(mux) serialize_equal(mux, 'mux(UInt<1>("h1"), b, c)')
def test_mux_tf_value_type_wrong(): mux = Mux(n("c", uw(1)), n("a", uw(7)), n("b", uw(8)), uw(8)) assert not check(mux) mux = Mux(n("c", uw(1)), n("a", uw(8)), n("b", sw(8)), uw(8)) assert not check(mux) mux = Mux(n("c", uw(1)), n("a", uw(8)), n("b", uw(8)), sw(8)) assert not check(mux)
def test_read_port_index_wrong(): mem_ref = n("m", vec(uw(8), 10)) mr = DefMemReadPort("mr", mem_ref, s(2, w(8)), n("clock", ClockType())) assert not check(mr) mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10)) mr = DefMemReadPort("mr", mem_ref, n("a", vec(uw(1), 10)), n("clock", ClockType())) assert not check(mr)
def test_bits(): basis_tester(bits_basis_cases) encounter_error_tester(bits_type_wrong_cases) encounter_error_tester(bits_width_wrong_cases) encounter_error_tester(bits_invalid_cases) serialize_equal(Bits(u(20, w(5)), [4, 4], uw(1)), 'bits(UInt<5>("h14"), 4, 4)') serialize_equal(Bits(s(-20, w(6)), [4, 3], uw(2)), 'bits(SInt<6>("h-14"), 4, 3)')
def test_write_port_index_wrong(): mem_ref = n("m", vec(uw(8), 10)) mw = DefMemWritePort("mw", mem_ref, s(2, w(8)), n("clock", ClockType())) assert not check(mw) mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10)) mw = DefMemWritePort("mw", mem_ref, n("a", vec(uw(1), 10)), n("clock", ClockType())) assert not check(mw)
def test_sub_field_basis(): bd = bdl(a=(uw(8), False), b=(sw(8), False)) sf = SubField(n("bd", bd), "a", uw(8)) assert check(sf) serialize_equal(sf, "bd.a") bd = bdl(a=(bdl(c=(uw(8), True)), False), b=(sw(8), False)) sf = SubField(n("bd", bd), "a", bdl(c=(uw(8), True))) assert check(sf) serialize_equal(sf, "bd.a")
def test_sub_access_basis(): vc = vec(uw(8), 10) sa = SubAccess(n("vc", vc), u(2, w(3)), uw(8)) assert check(sa) serialize_equal(sa, 'vc[UInt<3>("h2")]') vc = vec(uw(8), 10) sa = SubAccess(n("vc", vc), n("a", uw(8)), uw(8)) assert check(sa) serialize_equal(sa, 'vc[a]')