def test_2_Flow(self):
ut_testsrc = os.getenv("TESTSRC")
ly = pya.Layout()
ly.read(os.path.join(ut_testsrc, "testdata", "algo", "lvs_test_1.gds"))
lvs = pya.LayoutVsSchematic(pya.RecursiveShapeIterator(ly, ly.top_cell(), []))
nwell = lvs.make_layer(ly.layer(1, 0), "nwell")
active = lvs.make_layer(ly.layer(2, 0), "active")
pplus = lvs.make_layer(ly.layer(10, 0), "pplus")
nplus = lvs.make_layer(ly.layer(11, 0), "nplus")
poly = lvs.make_layer(ly.layer(3, 0), "poly")
poly_lbl = lvs.make_text_layer(ly.layer(3, 1), "poly_lbl")
diff_cont = lvs.make_layer(ly.layer(4, 0), "diff_cont")
poly_cont = lvs.make_layer(ly.layer(5, 0), "poly_cont")
metal1 = lvs.make_layer(ly.layer(6, 0), "metal1")
metal1_lbl = lvs.make_text_layer(ly.layer(6, 1), "metal1_lbl")
via1 = lvs.make_layer(ly.layer(7, 0), "via1")
metal2 = lvs.make_layer(ly.layer(8, 0), "metal2")
metal2_lbl = lvs.make_text_layer(ly.layer(8, 1), "metal2_lbl")
bulk = lvs.make_layer()
# compute some layers
active_in_nwell = active & nwell
pactive = active_in_nwell & pplus
ntie = active_in_nwell & nplus
pgate = pactive & poly
psd = pactive - pgate
active_outside_nwell = active - nwell
nactive = active_outside_nwell & nplus
ptie = active_outside_nwell & pplus
ngate = nactive & poly
nsd = nactive - ngate
# device extraction
pmos_ex = pya.DeviceExtractorMOS4Transistor("PMOS")
dl = { "SD": psd, "G": pgate, "P": poly, "W": nwell }
lvs.extract_devices(pmos_ex, dl)
nmos_ex = pya.DeviceExtractorMOS4Transistor("NMOS")
dl = { "SD": nsd, "G": ngate, "P": poly, "W": bulk }
lvs.extract_devices(nmos_ex, dl)
# register derived layers for connectivity
lvs.register(psd, "psd")
lvs.register(nsd, "nsd")
lvs.register(ptie, "ptie")
lvs.register(ntie, "ntie")
# intra-layer
lvs.connect(psd)
lvs.connect(nsd)
lvs.connect(nwell)
lvs.connect(poly)
lvs.connect(diff_cont)
lvs.connect(poly_cont)
lvs.connect(metal1)
lvs.connect(via1)
lvs.connect(metal2)
lvs.connect(ptie)
lvs.connect(ntie)
# inter-layer
lvs.connect(psd, diff_cont)
lvs.connect(nsd, diff_cont)
lvs.connect(poly, poly_cont)
lvs.connect(poly_cont, metal1)
lvs.connect(diff_cont, metal1)
lvs.connect(diff_cont, ptie)
lvs.connect(diff_cont, ntie)
lvs.connect(nwell, ntie)
lvs.connect(metal1, via1)
lvs.connect(via1, metal2)
lvs.connect(poly, poly_lbl) # attaches labels
lvs.connect(metal1, metal1_lbl) # attaches labels
lvs.connect(metal2, metal2_lbl) # attaches labels
# global
lvs.connect_global(ptie, "BULK")
lvs.connect_global(bulk, "BULK")
lvs.extract_netlist()
lvs.netlist().combine_devices()
lvs.netlist().make_top_level_pins()
lvs.netlist().purge()
# read the reference netlist
reader = pya.NetlistSpiceReader()
nl = pya.Netlist()
nl.read(os.path.join(ut_testsrc, "testdata", "algo", "lvs_test_1.spi"), reader)
self.assertEqual(lvs.reference == None, True)
lvs.reference = nl
self.assertEqual(lvs.reference == nl, True)
# do the actual compare
comparer = pya.NetlistComparer()
res = lvs.compare(comparer)
self.assertEqual(res, True)
self.assertEqual(lvs.xref != None, True)
def test_12_LayoutToNetlistExtractionWithDevicesAndGlobalNets(self):
ut_testsrc = os.getenv("TESTSRC")
ly = pya.Layout()
ly.read(
os.path.join(ut_testsrc, "testdata", "algo",
"device_extract_l3.gds"))
l2n = pya.LayoutToNetlist(
pya.RecursiveShapeIterator(ly, ly.top_cell(), []))
rbulk = l2n.make_layer("bulk")
rnwell = l2n.make_polygon_layer(ly.layer(1, 0), "nwell")
ractive = l2n.make_polygon_layer(ly.layer(2, 0), "active")
rpoly = l2n.make_polygon_layer(ly.layer(3, 0), "poly")
rpoly_lbl = l2n.make_text_layer(ly.layer(3, 1), "poly_lbl")
rdiff_cont = l2n.make_polygon_layer(ly.layer(4, 0), "diff_cont")
rpoly_cont = l2n.make_polygon_layer(ly.layer(5, 0), "poly_cont")
rmetal1 = l2n.make_polygon_layer(ly.layer(6, 0), "metal1")
rmetal1_lbl = l2n.make_text_layer(ly.layer(6, 1), "metal1_lbl")
rvia1 = l2n.make_polygon_layer(ly.layer(7, 0), "via1")
rmetal2 = l2n.make_polygon_layer(ly.layer(8, 0), "metal2")
rmetal2_lbl = l2n.make_text_layer(ly.layer(8, 1), "metal2_lbl")
rpplus = l2n.make_polygon_layer(ly.layer(10, 0), "pplus")
rnplus = l2n.make_polygon_layer(ly.layer(11, 0), "nplus")
ractive_in_nwell = ractive & rnwell
rpactive = ractive_in_nwell & rpplus
rntie = ractive_in_nwell & rnplus
rpgate = rpactive & rpoly
rpsd = rpactive - rpgate
ractive_outside_nwell = ractive - rnwell
rnactive = ractive_outside_nwell & rnplus
rptie = ractive_outside_nwell & rpplus
rngate = rnactive & rpoly
rnsd = rnactive - rngate
# PMOS transistor device extraction
pmos_ex = pya.DeviceExtractorMOS4Transistor("PMOS")
l2n.extract_devices(pmos_ex, {
"SD": rpsd,
"G": rpgate,
"P": rpoly,
"W": rnwell
})
# NMOS transistor device extraction
nmos_ex = pya.DeviceExtractorMOS4Transistor("NMOS")
l2n.extract_devices(nmos_ex, {
"SD": rnsd,
"G": rngate,
"P": rpoly,
"W": rbulk
})
# Define connectivity for netlist extraction
l2n.register(rpsd, "psd")
l2n.register(rnsd, "nsd")
l2n.register(rptie, "ptie")
l2n.register(rntie, "ntie")
# Intra-layer
l2n.connect(rpsd)
l2n.connect(rnsd)
l2n.connect(rnwell)
l2n.connect(rpoly)
l2n.connect(rdiff_cont)
l2n.connect(rpoly_cont)
l2n.connect(rmetal1)
l2n.connect(rvia1)
l2n.connect(rmetal2)
l2n.connect(rptie)
l2n.connect(rntie)
# Inter-layer
l2n.connect(rpsd, rdiff_cont)
l2n.connect(rnsd, rdiff_cont)
l2n.connect(rpoly, rpoly_cont)
l2n.connect(rpoly_cont, rmetal1)
l2n.connect(rdiff_cont, rmetal1)
l2n.connect(rdiff_cont, rntie)
l2n.connect(rdiff_cont, rptie)
l2n.connect(rnwell, rntie)
l2n.connect(rmetal1, rvia1)
l2n.connect(rvia1, rmetal2)
l2n.connect(rpoly, rpoly_lbl) # attaches labels
l2n.connect(rmetal1, rmetal1_lbl) # attaches labels
l2n.connect(rmetal2, rmetal2_lbl) # attaches labels
# Global connections
l2n.connect_global(rptie, "BULK")
l2n.connect_global(rbulk, "BULK")
# Perform netlist extraction
l2n.extract_netlist()
self.assertEqual(
str(l2n.netlist()), """circuit RINGO ();
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
end;
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
end;
circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device NMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
subcircuit TRANS $1 ($1=$3,$2=VSS,$3=IN);
subcircuit TRANS $2 ($1=$3,$2=VDD,$3=IN);
subcircuit TRANS $3 ($1=VDD,$2=OUT,$3=$3);
subcircuit TRANS $4 ($1=VSS,$2=OUT,$3=$3);
end;
circuit TRANS ($1=$1,$2=$2,$3=$3);
end;
""")
l2n.netlist().combine_devices()
l2n.netlist().make_top_level_pins()
l2n.netlist().purge()
self.assertEqual(
str(l2n.netlist()),
"""circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
end;
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
end;
circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device NMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
end;
""")
# cleanup now
l2n._destroy()
